[llvm] [X86][NFC] Move "_Int" after "k"/"kz" (PR #121450)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 1 19:42:43 PST 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-x86
Author: Phoebe Wang (phoebewang)
<details>
<summary>Changes</summary>
Address comment at https://github.com/llvm/llvm-project/pull/121373#discussion_r1900402932
---
Patch is 114.15 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/121450.diff
11 Files Affected:
- (modified) llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp (+6-6)
- (modified) llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp (+15-4)
- (modified) llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp (+6-6)
- (modified) llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp (+6-6)
- (modified) llvm/lib/Target/X86/X86InstrAVX10.td (+19-16)
- (modified) llvm/lib/Target/X86/X86InstrAVX512.td (+127-119)
- (modified) llvm/lib/Target/X86/X86InstrFMA3Info.cpp (+10-5)
- (modified) llvm/lib/Target/X86/X86InstrInfo.cpp (+147-147)
- (modified) llvm/lib/Target/X86/X86SchedSapphireRapids.td (+26-26)
- (modified) llvm/lib/Target/X86/X86ScheduleZnver4.td (+2-2)
- (modified) llvm/test/TableGen/x86-fold-tables.inc (+141-141)
``````````diff
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp
index b67c573e217ba4..abe0cc6365dd4e 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp
@@ -140,8 +140,8 @@ bool X86ATTInstPrinter::printVecCompareInstr(const MCInst *MI,
case X86::VCMPPSZ128rmik: case X86::VCMPPSZ128rrik:
case X86::VCMPPSZ256rmik: case X86::VCMPPSZ256rrik:
case X86::VCMPPSZrmik: case X86::VCMPPSZrrik:
- case X86::VCMPSDZrmi_Intk: case X86::VCMPSDZrri_Intk:
- case X86::VCMPSSZrmi_Intk: case X86::VCMPSSZrri_Intk:
+ case X86::VCMPSDZrmik_Int: case X86::VCMPSDZrrik_Int:
+ case X86::VCMPSSZrmik_Int: case X86::VCMPSSZrrik_Int:
case X86::VCMPPDZ128rmbi: case X86::VCMPPDZ128rmbik:
case X86::VCMPPDZ256rmbi: case X86::VCMPPDZ256rmbik:
case X86::VCMPPDZrmbi: case X86::VCMPPDZrmbik:
@@ -150,8 +150,8 @@ bool X86ATTInstPrinter::printVecCompareInstr(const MCInst *MI,
case X86::VCMPPSZrmbi: case X86::VCMPPSZrmbik:
case X86::VCMPPDZrrib: case X86::VCMPPDZrribk:
case X86::VCMPPSZrrib: case X86::VCMPPSZrribk:
- case X86::VCMPSDZrrib_Int: case X86::VCMPSDZrrib_Intk:
- case X86::VCMPSSZrrib_Int: case X86::VCMPSSZrrib_Intk:
+ case X86::VCMPSDZrrib_Int: case X86::VCMPSDZrribk_Int:
+ case X86::VCMPSSZrrib_Int: case X86::VCMPSSZrribk_Int:
case X86::VCMPPHZ128rmi: case X86::VCMPPHZ128rri:
case X86::VCMPPHZ256rmi: case X86::VCMPPHZ256rri:
case X86::VCMPPHZrmi: case X86::VCMPPHZrri:
@@ -160,12 +160,12 @@ bool X86ATTInstPrinter::printVecCompareInstr(const MCInst *MI,
case X86::VCMPPHZ128rmik: case X86::VCMPPHZ128rrik:
case X86::VCMPPHZ256rmik: case X86::VCMPPHZ256rrik:
case X86::VCMPPHZrmik: case X86::VCMPPHZrrik:
- case X86::VCMPSHZrmi_Intk: case X86::VCMPSHZrri_Intk:
+ case X86::VCMPSHZrmik_Int: case X86::VCMPSHZrrik_Int:
case X86::VCMPPHZ128rmbi: case X86::VCMPPHZ128rmbik:
case X86::VCMPPHZ256rmbi: case X86::VCMPPHZ256rmbik:
case X86::VCMPPHZrmbi: case X86::VCMPPHZrmbik:
case X86::VCMPPHZrrib: case X86::VCMPPHZrribk:
- case X86::VCMPSHZrrib_Int: case X86::VCMPSHZrrib_Intk:
+ case X86::VCMPSHZrrib_Int: case X86::VCMPSHZrribk_Int:
case X86::VCMPPBF16Z128rmi: case X86::VCMPPBF16Z128rri:
case X86::VCMPPBF16Z256rmi: case X86::VCMPPBF16Z256rri:
case X86::VCMPPBF16Zrmi: case X86::VCMPPBF16Zrri:
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp
index 9f8bc57fbc76d4..681d0dab37d09e 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp
@@ -40,6 +40,17 @@ using namespace llvm;
CASE_MASK_INS_COMMON(Inst, Suffix, src) \
CASE_MASKZ_INS_COMMON(Inst, Suffix, src)
+#define CASE_MASK_INS_COMMON_INT(Inst, Suffix, src) \
+ case X86::V##Inst##Suffix##src##k_Int:
+
+#define CASE_MASKZ_INS_COMMON_INT(Inst, Suffix, src) \
+ case X86::V##Inst##Suffix##src##kz_Int:
+
+#define CASE_AVX512_INS_COMMON_INT(Inst, Suffix, src) \
+ CASE_AVX_INS_COMMON(Inst, Suffix, src##_Int) \
+ CASE_MASK_INS_COMMON_INT(Inst, Suffix, src) \
+ CASE_MASKZ_INS_COMMON_INT(Inst, Suffix, src)
+
#define CASE_FPCLASS_PACKED(Inst, src) \
CASE_AVX_INS_COMMON(Inst, Z, src##i) \
CASE_AVX_INS_COMMON(Inst, Z256, src##i) \
@@ -196,8 +207,8 @@ using namespace llvm;
CASE_AVX_INS_COMMON(Inst##SS, , r_Int) \
CASE_AVX_INS_COMMON(Inst##SD, Z, r) \
CASE_AVX_INS_COMMON(Inst##SS, Z, r) \
- CASE_AVX512_INS_COMMON(Inst##SD, Z, r_Int) \
- CASE_AVX512_INS_COMMON(Inst##SS, Z, r_Int)
+ CASE_AVX512_INS_COMMON_INT(Inst##SD, Z, r) \
+ CASE_AVX512_INS_COMMON_INT(Inst##SS, Z, r)
#define CASE_FMA_SCALAR_MEM(Inst) \
CASE_AVX_INS_COMMON(Inst##SD, , m) \
@@ -206,8 +217,8 @@ using namespace llvm;
CASE_AVX_INS_COMMON(Inst##SS, , m_Int) \
CASE_AVX_INS_COMMON(Inst##SD, Z, m) \
CASE_AVX_INS_COMMON(Inst##SS, Z, m) \
- CASE_AVX512_INS_COMMON(Inst##SD, Z, m_Int) \
- CASE_AVX512_INS_COMMON(Inst##SS, Z, m_Int)
+ CASE_AVX512_INS_COMMON_INT(Inst##SD, Z, m) \
+ CASE_AVX512_INS_COMMON_INT(Inst##SS, Z, m)
#define CASE_FMA4(Inst, suf) \
CASE_AVX_INS_COMMON(Inst, 4, suf) \
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp
index fafcc737ff983d..01e2d4ace97733 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp
@@ -277,8 +277,8 @@ void X86InstPrinterCommon::printCMPMnemonic(const MCInst *MI, bool IsVCmp,
case X86::VCMPSDrmi_Int: case X86::VCMPSDrri_Int:
case X86::VCMPSDZrmi: case X86::VCMPSDZrri:
case X86::VCMPSDZrmi_Int: case X86::VCMPSDZrri_Int:
- case X86::VCMPSDZrmi_Intk: case X86::VCMPSDZrri_Intk:
- case X86::VCMPSDZrrib_Int: case X86::VCMPSDZrrib_Intk:
+ case X86::VCMPSDZrmik_Int: case X86::VCMPSDZrrik_Int:
+ case X86::VCMPSDZrrib_Int: case X86::VCMPSDZrribk_Int:
OS << "sd\t";
break;
case X86::CMPSSrmi: case X86::CMPSSrri:
@@ -287,8 +287,8 @@ void X86InstPrinterCommon::printCMPMnemonic(const MCInst *MI, bool IsVCmp,
case X86::VCMPSSrmi_Int: case X86::VCMPSSrri_Int:
case X86::VCMPSSZrmi: case X86::VCMPSSZrri:
case X86::VCMPSSZrmi_Int: case X86::VCMPSSZrri_Int:
- case X86::VCMPSSZrmi_Intk: case X86::VCMPSSZrri_Intk:
- case X86::VCMPSSZrrib_Int: case X86::VCMPSSZrrib_Intk:
+ case X86::VCMPSSZrmik_Int: case X86::VCMPSSZrrik_Int:
+ case X86::VCMPSSZrrib_Int: case X86::VCMPSSZrribk_Int:
OS << "ss\t";
break;
case X86::VCMPPHZ128rmi: case X86::VCMPPHZ128rri:
@@ -305,8 +305,8 @@ void X86InstPrinterCommon::printCMPMnemonic(const MCInst *MI, bool IsVCmp,
break;
case X86::VCMPSHZrmi: case X86::VCMPSHZrri:
case X86::VCMPSHZrmi_Int: case X86::VCMPSHZrri_Int:
- case X86::VCMPSHZrrib_Int: case X86::VCMPSHZrrib_Intk:
- case X86::VCMPSHZrmi_Intk: case X86::VCMPSHZrri_Intk:
+ case X86::VCMPSHZrrib_Int: case X86::VCMPSHZrribk_Int:
+ case X86::VCMPSHZrmik_Int: case X86::VCMPSHZrrik_Int:
OS << "sh\t";
break;
case X86::VCMPPBF16Z128rmi: case X86::VCMPPBF16Z128rri:
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp
index 680092679c9031..c26dc2ca5a7a4a 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp
@@ -119,8 +119,8 @@ bool X86IntelInstPrinter::printVecCompareInstr(const MCInst *MI, raw_ostream &OS
case X86::VCMPPSZ128rmik: case X86::VCMPPSZ128rrik:
case X86::VCMPPSZ256rmik: case X86::VCMPPSZ256rrik:
case X86::VCMPPSZrmik: case X86::VCMPPSZrrik:
- case X86::VCMPSDZrmi_Intk: case X86::VCMPSDZrri_Intk:
- case X86::VCMPSSZrmi_Intk: case X86::VCMPSSZrri_Intk:
+ case X86::VCMPSDZrmik_Int: case X86::VCMPSDZrrik_Int:
+ case X86::VCMPSSZrmik_Int: case X86::VCMPSSZrrik_Int:
case X86::VCMPPDZ128rmbi: case X86::VCMPPDZ128rmbik:
case X86::VCMPPDZ256rmbi: case X86::VCMPPDZ256rmbik:
case X86::VCMPPDZrmbi: case X86::VCMPPDZrmbik:
@@ -129,8 +129,8 @@ bool X86IntelInstPrinter::printVecCompareInstr(const MCInst *MI, raw_ostream &OS
case X86::VCMPPSZrmbi: case X86::VCMPPSZrmbik:
case X86::VCMPPDZrrib: case X86::VCMPPDZrribk:
case X86::VCMPPSZrrib: case X86::VCMPPSZrribk:
- case X86::VCMPSDZrrib_Int: case X86::VCMPSDZrrib_Intk:
- case X86::VCMPSSZrrib_Int: case X86::VCMPSSZrrib_Intk:
+ case X86::VCMPSDZrrib_Int: case X86::VCMPSDZrribk_Int:
+ case X86::VCMPSSZrrib_Int: case X86::VCMPSSZrribk_Int:
case X86::VCMPPHZ128rmi: case X86::VCMPPHZ128rri:
case X86::VCMPPHZ256rmi: case X86::VCMPPHZ256rri:
case X86::VCMPPHZrmi: case X86::VCMPPHZrri:
@@ -139,12 +139,12 @@ bool X86IntelInstPrinter::printVecCompareInstr(const MCInst *MI, raw_ostream &OS
case X86::VCMPPHZ128rmik: case X86::VCMPPHZ128rrik:
case X86::VCMPPHZ256rmik: case X86::VCMPPHZ256rrik:
case X86::VCMPPHZrmik: case X86::VCMPPHZrrik:
- case X86::VCMPSHZrmi_Intk: case X86::VCMPSHZrri_Intk:
+ case X86::VCMPSHZrmik_Int: case X86::VCMPSHZrrik_Int:
case X86::VCMPPHZ128rmbi: case X86::VCMPPHZ128rmbik:
case X86::VCMPPHZ256rmbi: case X86::VCMPPHZ256rmbik:
case X86::VCMPPHZrmbi: case X86::VCMPPHZrmbik:
case X86::VCMPPHZrrib: case X86::VCMPPHZrribk:
- case X86::VCMPSHZrrib_Int: case X86::VCMPSHZrrib_Intk:
+ case X86::VCMPSHZrrib_Int: case X86::VCMPSHZrribk_Int:
case X86::VCMPPBF16Z128rmi: case X86::VCMPPBF16Z128rri:
case X86::VCMPPBF16Z256rmi: case X86::VCMPPBF16Z256rri:
case X86::VCMPPBF16Zrmi: case X86::VCMPPBF16Zrri:
diff --git a/llvm/lib/Target/X86/X86InstrAVX10.td b/llvm/lib/Target/X86/X86InstrAVX10.td
index 3bc64eda01a9ce..cda6998778bc40 100644
--- a/llvm/lib/Target/X86/X86InstrAVX10.td
+++ b/llvm/lib/Target/X86/X86InstrAVX10.td
@@ -417,27 +417,30 @@ multiclass avx10_minmax_scalar<string OpStr, X86VectorVTInfo _, SDNode OpNode,
(i32 timm:$src3)))]>,
Sched<[WriteFMAX.Folded, WriteFMAX.ReadAfterFold]>;
}
- defm rri_Int : AVX512_maskable<0x53, MRMSrcReg, _, (outs VR128X:$dst),
- (ins VR128X:$src1, VR128X:$src2, i32u8imm:$src3),
- OpStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
- (_.VT (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
- (i32 timm:$src3)))>,
+ defm rri : AVX512_maskable<0x53, MRMSrcReg, _, (outs VR128X:$dst),
+ (ins VR128X:$src1, VR128X:$src2, i32u8imm:$src3),
+ OpStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
+ (_.VT (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
+ (i32 timm:$src3))),
+ 0, 0, 0, vselect_mask, "", "_Int">,
Sched<[WriteFMAX]>;
- defm rmi_Int : AVX512_maskable<0x53, MRMSrcMem, _, (outs VR128X:$dst),
- (ins VR128X:$src1, _.ScalarMemOp:$src2, i32u8imm:$src3),
- OpStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
- (_.VT (OpNode (_.VT _.RC:$src1), (_.ScalarIntMemFrags addr:$src2),
- (i32 timm:$src3)))>,
+ defm rmi : AVX512_maskable<0x53, MRMSrcMem, _, (outs VR128X:$dst),
+ (ins VR128X:$src1, _.ScalarMemOp:$src2, i32u8imm:$src3),
+ OpStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
+ (_.VT (OpNode (_.VT _.RC:$src1), (_.ScalarIntMemFrags addr:$src2),
+ (i32 timm:$src3))),
+ 0, 0, 0, vselect_mask, "", "_Int">,
Sched<[WriteFMAX.Folded, WriteFMAX.ReadAfterFold]>;
}
let Uses = []<Register>, mayRaiseFPException = 0 in
- defm rrib_Int : AVX512_maskable<0x53, MRMSrcReg, _, (outs VR128X:$dst),
- (ins VR128X:$src1, VR128X:$src2, i32u8imm:$src3),
- OpStr, "$src3, {sae}, $src2, $src1",
- "$src1, $src2, {sae}, $src3",
- (_.VT (OpNodeSAE (_.VT _.RC:$src1), (_.VT _.RC:$src2),
- (i32 timm:$src3)))>,
+ defm rrib : AVX512_maskable<0x53, MRMSrcReg, _, (outs VR128X:$dst),
+ (ins VR128X:$src1, VR128X:$src2, i32u8imm:$src3),
+ OpStr, "$src3, {sae}, $src2, $src1",
+ "$src1, $src2, {sae}, $src3",
+ (_.VT (OpNodeSAE (_.VT _.RC:$src1), (_.VT _.RC:$src2),
+ (i32 timm:$src3))),
+ 0, 0, 0, vselect_mask, "", "_Int">,
Sched<[WriteFMAX]>, EVEX_B;
}
}
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td
index e899807cd1b7c5..d6ca4b142afe0a 100644
--- a/llvm/lib/Target/X86/X86InstrAVX512.td
+++ b/llvm/lib/Target/X86/X86InstrAVX512.td
@@ -28,19 +28,20 @@ multiclass AVX512_maskable_custom<bits<8> O, Format F,
bit IsCommutable = 0,
bit IsKCommutable = 0,
bit IsKZCommutable = IsCommutable,
- string ClobberConstraint = ""> {
+ string ClobberConstraint = "",
+ string Suffix = ""> {
let isCommutable = IsCommutable, Constraints = ClobberConstraint in
- def NAME: AVX512<O, F, Outs, Ins,
- OpcodeStr#"\t{"#AttSrcAsm#", $dst|"#
- "$dst, "#IntelSrcAsm#"}",
- Pattern>;
+ def Suffix: AVX512<O, F, Outs, Ins,
+ OpcodeStr#"\t{"#AttSrcAsm#", $dst|"#
+ "$dst, "#IntelSrcAsm#"}",
+ Pattern>;
// Prefer over VMOV*rrk Pat<>
let isCommutable = IsKCommutable in
- def NAME#k: AVX512<O, F, Outs, MaskingIns,
- OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}|"#
- "$dst {${mask}}, "#IntelSrcAsm#"}",
- MaskingPattern>,
+ def k#Suffix: AVX512<O, F, Outs, MaskingIns,
+ OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}|"#
+ "$dst {${mask}}, "#IntelSrcAsm#"}",
+ MaskingPattern>,
EVEX_K {
// In case of the 3src subclass this is overridden with a let.
string Constraints = !if(!eq(ClobberConstraint, ""), MaskingConstraint,
@@ -52,10 +53,10 @@ multiclass AVX512_maskable_custom<bits<8> O, Format F,
// So, it is Ok to use IsCommutable instead of IsKCommutable.
let isCommutable = IsKZCommutable, // Prefer over VMOV*rrkz Pat<>
Constraints = ClobberConstraint in
- def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
- OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}|"#
- "$dst {${mask}} {z}, "#IntelSrcAsm#"}",
- ZeroMaskingPattern>,
+ def kz#Suffix: AVX512<O, F, Outs, ZeroMaskingIns,
+ OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}|"#
+ "$dst {${mask}} {z}, "#IntelSrcAsm#"}",
+ ZeroMaskingPattern>,
EVEX_KZ;
}
@@ -72,7 +73,8 @@ multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
bit IsCommutable = 0,
bit IsKCommutable = 0,
bit IsKZCommutable = IsCommutable,
- string ClobberConstraint = ""> :
+ string ClobberConstraint = "",
+ string Suffix = ""> :
AVX512_maskable_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
AttSrcAsm, IntelSrcAsm,
[(set _.RC:$dst, RHS)],
@@ -80,7 +82,8 @@ multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
[(set _.RC:$dst,
(Select _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
MaskingConstraint, IsCommutable,
- IsKCommutable, IsKZCommutable, ClobberConstraint>;
+ IsKCommutable, IsKZCommutable, ClobberConstraint,
+ Suffix>;
// This multiclass generates the unconditional/non-masking, the masking and
// the zero-masking variant of the vector instruction. In the masking case, the
@@ -115,23 +118,24 @@ multiclass AVX512_maskable<bits<8> O, Format F, X86VectorVTInfo _,
bit IsCommutable = 0, bit IsKCommutable = 0,
bit IsKZCommutable = IsCommutable,
SDPatternOperator Select = vselect_mask,
- string ClobberConstraint = ""> :
+ string ClobberConstraint = "",
+ string Suffix = ""> :
AVX512_maskable_common<O, F, _, Outs, Ins,
!con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
!con((ins _.KRCWM:$mask), Ins),
OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
(Select _.KRCWM:$mask, RHS, _.RC:$src0),
Select, "$src0 = $dst", IsCommutable, IsKCommutable,
- IsKZCommutable, ClobberConstraint>;
+ IsKZCommutable, ClobberConstraint, Suffix>;
// This multiclass generates the unconditional/non-masking, the masking and
// the zero-masking variant of the scalar instruction.
multiclass AVX512_maskable_scalar<bits<8> O, Format F, X86VectorVTInfo _,
dag Outs, dag Ins, string OpcodeStr,
string AttSrcAsm, string IntelSrcAsm,
- dag RHS> :
+ dag RHS, string Suffix = ""> :
AVX512_maskable<O, F, _, Outs, Ins, OpcodeStr, AttSrcAsm, IntelSrcAsm,
- RHS, 0, 0, 0, X86selects_mask>;
+ RHS, 0, 0, 0, X86selects_mask, "", Suffix>;
// Similar to AVX512_maskable but in this case one of the source operands
// ($src1) is already tied to $dst so we just use that for the preserved
@@ -144,7 +148,7 @@ multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _,
bit IsCommutable = 0,
bit IsKCommutable = 0,
SDPatternOperator Select = vselect_mask,
- bit MaskOnly = 0> :
+ bit MaskOnly = 0, string Suffix = ""> :
AVX512_maskable_common<O, F, _, Outs,
!con((ins _.RC:$src1), NonTiedIns),
!con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
@@ -152,7 +156,8 @@ multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _,
OpcodeStr, AttSrcAsm, IntelSrcAsm,
!if(MaskOnly, (null_frag), RHS),
(Select _.KRCWM:$mask, RHS, _.RC:$src1),
- Select, "", IsCommutable, IsKCommutable>;
+ Select, "", IsCommutable, IsKCommutable,
+ IsCommutable, "", Suffix>;
// Similar to AVX512_maskable_3src but in this case the input VT for the tied
// operand differs from the output VT. This requires a bitconvert on
@@ -178,10 +183,10 @@ multiclass AVX512_maskable_3src_scalar<bits<8> O, Format F, X86VectorVTInfo _,
dag RHS,
bit IsCommutable = 0,
bit IsKCommutable = 0,
- bit MaskOnly = 0> :
+ bit MaskOnly = 0, string Suffix = ""> :
AVX512_maskable_3src<O, F, _, Outs, NonTiedIns, OpcodeStr, AttSrcAsm,
IntelSrcAsm, RHS, IsCommutable, IsKCommutable,
- X86selects_mask, MaskOnly>;
+ X86selects_mask, MaskOnly, Suffix>;
multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
dag Outs, dag Ins,
@@ -215,17 +220,18 @@ multiclass AVX512_maskable_custom_cmp<bits<8> O, Format F,
string AttSrcAsm, string IntelSrcAsm,
list<dag> P...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/121450
More information about the llvm-commits
mailing list