[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)

[Craig Topper via llvm-commits]

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@@ -389,6 +390,13 @@ class RISCVPassConfig : public TargetPassConfig {
       DAG->addMutation(createStoreClusterDAGMutation(
           DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));
     }
+
+    const RISCVSubtarget &ST = C->MF->getSubtarget<RISCVSubtarget>();
+    if (!ST.getMacroFusions().empty() && ST.useLoadStorePairs()) {
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topperc wrote:

This needs to be integrated with the `EnablePostMISchedLoadStoreClustering` on line 386. Otherwise we will have multiple load/store cluster mutations.

https://github.com/llvm/llvm-project/pull/121394