[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)

[Craig Topper via llvm-commits]

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@@ -257,6 +257,146 @@ def simm12 : RISCVSImmLeafOp<12> {
   }];
 }
 
+// A 7-bit unsigned immediate where the least significant two bits are zero.
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topperc wrote:

Why do these need to move? RISCVInstrInfoXMips.td is included after RISCVInstrInfoC.td

https://github.com/llvm/llvm-project/pull/121394