[llvm] 50a457d - [RISCV][VLOPT] Add getOperandInfo for saturating signed multiply (#120351)

[via llvm-commits]

Author: Michael Maitland
Date: 2024-12-30T09:00:27-05:00
New Revision: 50a457d9e89142e89a9b66de5c23c515b50d1f96

URL: https://github.com/llvm/llvm-project/commit/50a457d9e89142e89a9b66de5c23c515b50d1f96
DIFF: https://github.com/llvm/llvm-project/commit/50a457d9e89142e89a9b66de5c23c515b50d1f96.diff

LOG: [RISCV][VLOPT] Add getOperandInfo for saturating signed multiply (#120351)

These instructions are covered by the existing tests. We don't add them to
isSupported because of VXSAT. This decision was made in #120358.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
index 4e3212c70ee9b0..85ea5a23e8f293 100644
--- a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
@@ -415,6 +415,11 @@ static OperandInfo getOperandInfo(const MachineOperand &MO,
   case RISCV::VASUBU_VX:
   case RISCV::VASUB_VV:
   case RISCV::VASUB_VX:
+  // Vector Single-Width Fractional Multiply with Rounding and Saturation
+  // EEW=SEW. EMUL=LMUL. The instruction produces 2*SEW product internally but
+  // saturates to fit into SEW bits.
+  case RISCV::VSMUL_VV:
+  case RISCV::VSMUL_VX:
   // Vector Single-Width Scaling Shift Instructions
   // EEW=SEW. EMUL=LMUL.
   case RISCV::VSSRL_VI: