[llvm] select v_sat_pk from two i16 or v2i16 (PR #121124)
via llvm-commits
llvm-commits at lists.llvm.org
Sun Dec 29 18:04:44 PST 2024
https://github.com/Shoreshen updated https://github.com/llvm/llvm-project/pull/121124
>From 7e8c98b635b825cbd94da43a8fd53d86a4254de5 Mon Sep 17 00:00:00 2001
From: shore <372660931 at qq.com>
Date: Thu, 26 Dec 2024 10:00:33 +0800
Subject: [PATCH 1/6] select v_sat_pk from 2 i16
---
llvm/lib/Target/AMDGPU/AMDGPUInstructions.td | 14 ++++++++++++++
llvm/lib/Target/AMDGPU/SIInstructions.td | 12 ++++++++++++
2 files changed, 26 insertions(+)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
index 6a5065cd4a0e8f..0a7747b8736786 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
@@ -315,6 +315,20 @@ def srl_16 : PatFrag<
(ops node:$src0), (srl_oneuse node:$src0, (i32 16))
>;
+def clamp_s16_u8 : PatFrag<
+ (ops node:$src),
+ (i16 (AMDGPUsmed3 $src, (i16 0), (i16 255)))
+>;
+
+def conc_lo_u8_i16 : PatFrags<
+ (ops node:$src0, node:$src1),
+ [
+ (or
+ (and (i16 $src0), (i16 255)),
+ (shl (i16 $src1), (i16 8))
+ )
+ ]
+>;
def hi_i16_elt : PatFrag<
(ops node:$src0), (i16 (trunc (i32 (srl_16 node:$src0))))
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index 789ce8815cf801..c0dd87fccfb7bb 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -3298,6 +3298,18 @@ def : GCNPat <
(v2i16 (V_LSHL_OR_B32_e64 $src1, (i32 16), (i32 (V_AND_B32_e64 (i32 (V_MOV_B32_e32 (i32 0xffff))), $src0))))
>;
+multiclass V_SAT_PK_Pat<Instruction inst> {
+ def: GCNPat<
+ (i16 (conc_lo_u8_i16 (clamp_s16_u8 i16:$lo), (clamp_s16_u8 i16:$hi))),
+ (inst
+ (V_LSHL_OR_B32_e64 VGPR_32:$hi, (S_MOV_B32 (i32 16)),
+ (V_AND_B32_e64 VGPR_32:$lo, (S_MOV_B32 (i32 0xFFFF)))))
+ >;
+}
+
+let OtherPredicates = [NotHasTrue16BitInsts] in
+defm : V_SAT_PK_Pat<V_SAT_PK_U8_I16_e64>;
+
// With multiple uses of the shift, this will duplicate the shift and
// increase register pressure.
def : GCNPat <
>From a6c8b45252df1fd1d2c17d79fd687903a784a7cb Mon Sep 17 00:00:00 2001
From: shore <372660931 at qq.com>
Date: Thu, 26 Dec 2024 12:49:27 +0800
Subject: [PATCH 2/6] add test, update pattern
---
llvm/lib/Target/AMDGPU/AMDGPUInstructions.td | 2 +-
llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll | 39 ++++++++++++++++++++
2 files changed, 40 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
index 0a7747b8736786..79a68c9c452ae6 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
@@ -324,7 +324,7 @@ def conc_lo_u8_i16 : PatFrags<
(ops node:$src0, node:$src1),
[
(or
- (and (i16 $src0), (i16 255)),
+ (i16 $src0),
(shl (i16 $src1), (i16 8))
)
]
diff --git a/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll b/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
index b919bf0605a121..5a42e5d64906f6 100644
--- a/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
@@ -587,5 +587,44 @@ define <2 x i16> @vec_smin_smax(<2 x i16> %src) {
%src.clamp = call <2 x i16> @llvm.smax.v2i16(<2 x i16> %src.min, <2 x i16> <i16 0, i16 0>)
ret <2 x i16> %src.clamp
}
+define i16 @basic_smax_smin_bitop(i16 %src0, i16 %src1) {
+; SDAG-VI-LABEL: basic_smax_smin_bitop:
+; SDAG-VI: ; %bb.0:
+; SDAG-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-VI-NEXT: v_max_i16_e32 v0, 0, v0
+; SDAG-VI-NEXT: v_max_i16_e32 v1, 0, v1
+; SDAG-VI-NEXT: v_mov_b32_e32 v2, 0xff
+; SDAG-VI-NEXT: v_min_i16_e32 v0, 0xff, v0
+; SDAG-VI-NEXT: v_min_i16_sdwa v1, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; SDAG-VI-NEXT: v_or_b32_e32 v0, v0, v1
+; SDAG-VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX9-LABEL: basic_smax_smin_bitop:
+; GISEL-GFX9: ; %bb.0:
+; GISEL-GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GISEL-GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GISEL-GFX9-NEXT: v_sat_pk_u8_i16_e32 v0, v0
+; GISEL-GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX11-LABEL: basic_smax_smin_bitop:
+; GISEL-GFX11: ; %bb.0:
+; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX11-NEXT: v_med3_i16 v1, v1, 0, 0xff
+; GISEL-GFX11-NEXT: v_med3_i16 v0, v0, 0, 0xff
+; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GISEL-GFX11-NEXT: v_lshlrev_b16 v1, 8, v1
+; GISEL-GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; GISEL-GFX11-NEXT: s_setpc_b64 s[30:31]
+
+ %src0.max = call i16 @llvm.smax.i16(i16 %src0, i16 0)
+ %src0.clamp = call i16 @llvm.smin.i16(i16 %src0.max, i16 255)
+ %src1.max = call i16 @llvm.smax.i16(i16 %src1, i16 0)
+ %src1.clamp = call i16 @llvm.smin.i16(i16 %src1.max, i16 255)
+ %src0.and = and i16 %src0.clamp, 255
+ %src1.shl = shl i16 %src1.clamp, 8
+ %or = or i16 %src0.and, %src1.shl
+ ret i16 %or
+}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GFX11: {{.*}}
>From 4a6157224fcd04e05e4e03de47ac9a59200d9279 Mon Sep 17 00:00:00 2001
From: shore <372660931 at qq.com>
Date: Thu, 26 Dec 2024 19:09:36 +0800
Subject: [PATCH 3/6] add more cases and patters
---
llvm/lib/Target/AMDGPU/AMDGPUInstructions.td | 39 ++-
llvm/lib/Target/AMDGPU/SIInstructions.td | 24 +-
llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll | 248 ++++++++++++++++++-
3 files changed, 294 insertions(+), 17 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
index 79a68c9c452ae6..918ea19276dcbd 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
@@ -321,13 +321,38 @@ def clamp_s16_u8 : PatFrag<
>;
def conc_lo_u8_i16 : PatFrags<
- (ops node:$src0, node:$src1),
- [
- (or
- (i16 $src0),
- (shl (i16 $src1), (i16 8))
- )
- ]
+ (ops node:$src0, node:$src1),
+ [
+ (or
+ (i16 $src0),
+ (shl (i16 $src1), (i16 8))
+ ),
+ (or
+ (and (i16 $src0), (i16 255)),
+ (shl (i16 $src1), (i16 8))
+ ),
+ ]
+>;
+
+def clamp_v2i16_u8 : PatFrags<
+ (ops node:$src),
+ [
+ (v2i16 (smax (smin $src, (build_vector (i16 255), (i16 255))), (build_vector (i16 0), (i16 0)))),
+ (v2i16 (smin (smax $src, (build_vector (i16 255), (i16 255))), (build_vector (i16 0), (i16 0))))
+ ]
+>;
+
+def conc_lo_v2i16_i16 : PatFrags<
+ (ops node:$src),
+ [
+ (or
+ (i16 (trunc (i32 (bitconvert $src)))),
+ (shl
+ (i16 (trunc(srl (i32 (bitconvert $src)), (i32 16)))),
+ (i16 8)
+ )
+ )
+ ]
>;
def hi_i16_elt : PatFrag<
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index c0dd87fccfb7bb..5e491e1fcea7ec 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -3299,12 +3299,24 @@ def : GCNPat <
>;
multiclass V_SAT_PK_Pat<Instruction inst> {
- def: GCNPat<
- (i16 (conc_lo_u8_i16 (clamp_s16_u8 i16:$lo), (clamp_s16_u8 i16:$hi))),
- (inst
- (V_LSHL_OR_B32_e64 VGPR_32:$hi, (S_MOV_B32 (i32 16)),
- (V_AND_B32_e64 VGPR_32:$lo, (S_MOV_B32 (i32 0xFFFF)))))
- >;
+ def: GCNPat<
+ (i16 (conc_lo_u8_i16 (clamp_s16_u8 i16:$lo), (clamp_s16_u8 i16:$hi))),
+ (inst
+ (V_LSHL_OR_B32_e64 VGPR_32:$hi, (S_MOV_B32 (i32 16)),
+ (V_AND_B32_e64 VGPR_32:$lo, (S_MOV_B32 (i32 0xFFFF)))))
+ >;
+
+ def: GCNPat<
+ (i16 (conc_lo_u8_i16 (clamp_s16_u8 i16:$lo), (smax i16:$hi, (i16 0)))),
+ (inst
+ (V_LSHL_OR_B32_e64 VGPR_32:$hi, (S_MOV_B32 (i32 16)),
+ (V_AND_B32_e64 VGPR_32:$lo, (S_MOV_B32 (i32 0xFFFF)))))
+ >;
+
+ def: GCNPat<
+ (i16 (conc_lo_v2i16_i16 (clamp_v2i16_u8 v2i16:$src))),
+ (inst VGPR_32:$src)
+ >;
}
let OtherPredicates = [NotHasTrue16BitInsts] in
diff --git a/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll b/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
index 5a42e5d64906f6..feb4bd73e39ba3 100644
--- a/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
@@ -587,8 +587,8 @@ define <2 x i16> @vec_smin_smax(<2 x i16> %src) {
%src.clamp = call <2 x i16> @llvm.smax.v2i16(<2 x i16> %src.min, <2 x i16> <i16 0, i16 0>)
ret <2 x i16> %src.clamp
}
-define i16 @basic_smax_smin_bitop(i16 %src0, i16 %src1) {
-; SDAG-VI-LABEL: basic_smax_smin_bitop:
+define i16 @basic_smax_smin_bit_or(i16 %src0, i16 %src1) {
+; SDAG-VI-LABEL: basic_smax_smin_bit_or:
; SDAG-VI: ; %bb.0:
; SDAG-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SDAG-VI-NEXT: v_max_i16_e32 v0, 0, v0
@@ -599,7 +599,36 @@ define i16 @basic_smax_smin_bitop(i16 %src0, i16 %src1) {
; SDAG-VI-NEXT: v_or_b32_e32 v0, v0, v1
; SDAG-VI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX9-LABEL: basic_smax_smin_bitop:
+; SDAG-GFX9-LABEL: basic_smax_smin_bit_or:
+; SDAG-GFX9: ; %bb.0:
+; SDAG-GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SDAG-GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; SDAG-GFX9-NEXT: v_sat_pk_u8_i16_e32 v0, v0
+; SDAG-GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX11-LABEL: basic_smax_smin_bit_or:
+; SDAG-GFX11: ; %bb.0:
+; SDAG-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX11-NEXT: v_med3_i16 v1, v1, 0, 0xff
+; SDAG-GFX11-NEXT: v_med3_i16 v0, v0, 0, 0xff
+; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; SDAG-GFX11-NEXT: v_lshlrev_b16 v1, 8, v1
+; SDAG-GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; SDAG-GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-VI-LABEL: basic_smax_smin_bit_or:
+; GISEL-VI: ; %bb.0:
+; GISEL-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-VI-NEXT: v_max_i16_e32 v0, 0, v0
+; GISEL-VI-NEXT: v_mov_b32_e32 v2, 0xff
+; GISEL-VI-NEXT: v_max_i16_e32 v1, 0, v1
+; GISEL-VI-NEXT: v_min_i16_e32 v0, 0xff, v0
+; GISEL-VI-NEXT: v_min_i16_sdwa v1, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GISEL-VI-NEXT: v_or_b32_e32 v0, v0, v1
+; GISEL-VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX9-LABEL: basic_smax_smin_bit_or:
; GISEL-GFX9: ; %bb.0:
; GISEL-GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
@@ -607,7 +636,7 @@ define i16 @basic_smax_smin_bitop(i16 %src0, i16 %src1) {
; GISEL-GFX9-NEXT: v_sat_pk_u8_i16_e32 v0, v0
; GISEL-GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX11-LABEL: basic_smax_smin_bitop:
+; GISEL-GFX11-LABEL: basic_smax_smin_bit_or:
; GISEL-GFX11: ; %bb.0:
; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-GFX11-NEXT: v_med3_i16 v1, v1, 0, 0xff
@@ -626,5 +655,216 @@ define i16 @basic_smax_smin_bitop(i16 %src0, i16 %src1) {
%or = or i16 %src0.and, %src1.shl
ret i16 %or
}
+define i16 @basic_smax_smin_vec_cast(i16 %src0, i16 %src1) {
+;; SDAG-VI-LABEL: basic_smax_smin_vec_cast:
+; SDAG-VI: ; %bb.0:
+; SDAG-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-VI-NEXT: v_max_i16_e32 v0, 0, v0
+; SDAG-VI-NEXT: v_max_i16_e32 v1, 0, v1
+; SDAG-VI-NEXT: v_mov_b32_e32 v2, 0xff
+; SDAG-VI-NEXT: v_min_i16_e32 v0, 0xff, v0
+; SDAG-VI-NEXT: v_min_i16_sdwa v1, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; SDAG-VI-NEXT: v_or_b32_e32 v0, v0, v1
+; SDAG-VI-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX9-LABEL: basic_smax_smin_vec_cast:
+; SDAG-GFX9: ; %bb.0:
+; SDAG-GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SDAG-GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; SDAG-GFX9-NEXT: v_sat_pk_u8_i16_e32 v0, v0
+; SDAG-GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX11-LABEL: basic_smax_smin_vec_cast:
+; SDAG-GFX11: ; %bb.0:
+; SDAG-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX11-NEXT: v_med3_i16 v1, v1, 0, 0xff
+; SDAG-GFX11-NEXT: v_med3_i16 v0, v0, 0, 0xff
+; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; SDAG-GFX11-NEXT: v_lshlrev_b16 v1, 8, v1
+; SDAG-GFX11-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; SDAG-GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; SDAG-GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-VI-LABEL: basic_smax_smin_vec_cast:
+; GISEL-VI: ; %bb.0:
+; GISEL-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-VI-NEXT: v_max_i16_e32 v0, 0, v0
+; GISEL-VI-NEXT: v_mov_b32_e32 v2, 0xff
+; GISEL-VI-NEXT: v_max_i16_e32 v1, 0, v1
+; GISEL-VI-NEXT: v_min_i16_e32 v0, 0xff, v0
+; GISEL-VI-NEXT: v_min_i16_sdwa v1, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GISEL-VI-NEXT: v_or_b32_e32 v0, v0, v1
+; GISEL-VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX9-LABEL: basic_smax_smin_vec_cast:
+; GISEL-GFX9: ; %bb.0:
+; GISEL-GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GISEL-GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GISEL-GFX9-NEXT: v_sat_pk_u8_i16_e32 v0, v0
+; GISEL-GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX11-LABEL: basic_smax_smin_vec_cast:
+; GISEL-GFX11: ; %bb.0:
+; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX11-NEXT: v_med3_i16 v1, v1, 0, 0xff
+; GISEL-GFX11-NEXT: v_med3_i16 v0, v0, 0, 0xff
+; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GISEL-GFX11-NEXT: v_lshlrev_b16 v1, 8, v1
+; GISEL-GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; GISEL-GFX11-NEXT: s_setpc_b64 s[30:31]
+
+ %src0.max = call i16 @llvm.smax.i16(i16 %src0, i16 0)
+ %src0.clamp = call i16 @llvm.smin.i16(i16 %src0.max, i16 255)
+ %src1.max = call i16 @llvm.smax.i16(i16 %src1, i16 0)
+ %src1.clamp = call i16 @llvm.smin.i16(i16 %src1.max, i16 255)
+ %insert.0 = insertelement <2 x i16> undef, i16 %src0.clamp, i32 0
+ %vec = insertelement <2 x i16> %insert.0, i16 %src1.clamp, i32 1
+ %vec.trunc = trunc <2 x i16> %vec to <2 x i8>
+ %cast = bitcast <2 x i8> %vec.trunc to i16
+ ret i16 %cast
+}
+define i16 @basic_smax_smin_bit_shl(i16 %src0, i16 %src1) {
+; SDAG-VI-LABEL: basic_smax_smin_bit_shl:
+; SDAG-VI: ; %bb.0:
+; SDAG-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-VI-NEXT: v_max_i16_e32 v0, 0, v0
+; SDAG-VI-NEXT: v_mov_b32_e32 v2, 0
+; SDAG-VI-NEXT: v_min_i16_e32 v0, 0xff, v0
+; SDAG-VI-NEXT: v_max_i16_sdwa v1, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; SDAG-VI-NEXT: v_or_b32_e32 v0, v0, v1
+; SDAG-VI-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX9-LABEL: basic_smax_smin_bit_shl:
+; SDAG-GFX9: ; %bb.0:
+; SDAG-GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SDAG-GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; SDAG-GFX9-NEXT: v_sat_pk_u8_i16_e32 v0, v0
+; SDAG-GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX11-LABEL: basic_smax_smin_bit_shl:
+; SDAG-GFX11: ; %bb.0:
+; SDAG-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX11-NEXT: v_max_i16 v1, v1, 0
+; SDAG-GFX11-NEXT: v_med3_i16 v0, v0, 0, 0xff
+; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; SDAG-GFX11-NEXT: v_lshlrev_b16 v1, 8, v1
+; SDAG-GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; SDAG-GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-VI-LABEL: basic_smax_smin_bit_shl:
+; GISEL-VI: ; %bb.0:
+; GISEL-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-VI-NEXT: v_max_i16_e32 v0, 0, v0
+; GISEL-VI-NEXT: v_mov_b32_e32 v2, 0
+; GISEL-VI-NEXT: v_min_i16_e32 v0, 0xff, v0
+; GISEL-VI-NEXT: v_max_i16_sdwa v1, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GISEL-VI-NEXT: v_or_b32_e32 v0, v0, v1
+; GISEL-VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX9-LABEL: basic_smax_smin_bit_shl:
+; GISEL-GFX9: ; %bb.0:
+; GISEL-GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GISEL-GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GISEL-GFX9-NEXT: v_sat_pk_u8_i16_e32 v0, v0
+; GISEL-GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX11-LABEL: basic_smax_smin_bit_shl:
+; GISEL-GFX11: ; %bb.0:
+; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX11-NEXT: v_max_i16 v1, v1, 0
+; GISEL-GFX11-NEXT: v_med3_i16 v0, v0, 0, 0xff
+; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GISEL-GFX11-NEXT: v_lshlrev_b16 v1, 8, v1
+; GISEL-GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; GISEL-GFX11-NEXT: s_setpc_b64 s[30:31]
+
+ %src0.max = call i16 @llvm.smax.i16(i16 %src0, i16 0)
+ %src0.clamp = call i16 @llvm.smin.i16(i16 %src0.max, i16 255)
+ %src1.max = call i16 @llvm.smax.i16(i16 %src1, i16 0)
+ %src1.shl = shl i16 %src1.max, 8
+ %or = or i16 %src0.clamp, %src1.shl
+ ret i16 %or
+}
+define i16 @basic_smax_smin_vec_input(<2 x i16> %src) {
+; SDAG-VI-LABEL: basic_smax_smin_vec_input:
+; SDAG-VI: ; %bb.0:
+; SDAG-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-VI-NEXT: v_mov_b32_e32 v1, 0xff
+; SDAG-VI-NEXT: v_min_i16_sdwa v1, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; SDAG-VI-NEXT: v_min_i16_e32 v0, 0xff, v0
+; SDAG-VI-NEXT: v_mov_b32_e32 v2, 0
+; SDAG-VI-NEXT: v_max_i16_e32 v0, 0, v0
+; SDAG-VI-NEXT: v_max_i16_sdwa v1, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; SDAG-VI-NEXT: v_or_b32_e32 v0, v0, v1
+; SDAG-VI-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX9-LABEL: basic_smax_smin_vec_input:
+; SDAG-GFX9: ; %bb.0:
+; SDAG-GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX9-NEXT: v_sat_pk_u8_i16_e32 v0, v0
+; SDAG-GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX11-LABEL: basic_smax_smin_vec_input:
+; SDAG-GFX11: ; %bb.0:
+; SDAG-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX11-NEXT: v_pk_min_i16 v0, 0xff, v0 op_sel_hi:[0,1]
+; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; SDAG-GFX11-NEXT: v_pk_max_i16 v0, v0, 0
+; SDAG-GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; SDAG-GFX11-NEXT: v_lshlrev_b16 v1, 8, v1
+; SDAG-GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; SDAG-GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-VI-LABEL: basic_smax_smin_vec_input:
+; GISEL-VI: ; %bb.0:
+; GISEL-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-VI-NEXT: v_mov_b32_e32 v1, 0xff
+; GISEL-VI-NEXT: v_min_i16_e32 v2, 0xff, v0
+; GISEL-VI-NEXT: v_min_i16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GISEL-VI-NEXT: v_max_i16_e32 v0, 0, v0
+; GISEL-VI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GISEL-VI-NEXT: v_max_i16_e32 v1, 0, v2
+; GISEL-VI-NEXT: v_lshlrev_b16_e32 v0, 8, v0
+; GISEL-VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GISEL-VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX9-LABEL: basic_smax_smin_vec_input:
+; GISEL-GFX9: ; %bb.0:
+; GISEL-GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, 0xff00ff
+; GISEL-GFX9-NEXT: v_pk_min_i16 v0, v1, v0
+; GISEL-GFX9-NEXT: v_pk_max_i16 v0, 0, v0
+; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, 0xff
+; GISEL-GFX9-NEXT: v_and_b32_sdwa v1, v0, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GISEL-GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GISEL-GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX11-LABEL: basic_smax_smin_vec_input:
+; GISEL-GFX11: ; %bb.0:
+; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX11-NEXT: v_pk_min_i16 v0, 0xff00ff, v0
+; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GISEL-GFX11-NEXT: v_pk_max_i16 v0, 0, v0
+; GISEL-GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GISEL-GFX11-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GISEL-GFX11-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GISEL-GFX11-NEXT: v_lshlrev_b16 v1, 8, v1
+; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; GISEL-GFX11-NEXT: s_setpc_b64 s[30:31]
+
+ %smin = call <2 x i16> @llvm.smin.v2i16(<2 x i16> <i16 255, i16 255>, <2 x i16> %src)
+ %smed = call <2 x i16> @llvm.smax.v2i16(<2 x i16> <i16 0, i16 0>, <2 x i16> %smin)
+ %vec.trunc = trunc <2 x i16> %smed to <2 x i8>
+ %cast = bitcast <2 x i8> %vec.trunc to i16
+ ret i16 %cast
+}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GFX11: {{.*}}
>From 0b5e7ee312486dc761a54e0efdee3673d5db10e6 Mon Sep 17 00:00:00 2001
From: shore <372660931 at qq.com>
Date: Thu, 26 Dec 2024 23:14:26 +0800
Subject: [PATCH 4/6] fix bug and add case
---
llvm/lib/Target/AMDGPU/AMDGPUInstructions.td | 2 +-
llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll | 76 ++++++++++++++++++++
2 files changed, 77 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
index 918ea19276dcbd..230c2fff5f3196 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
@@ -338,7 +338,7 @@ def clamp_v2i16_u8 : PatFrags<
(ops node:$src),
[
(v2i16 (smax (smin $src, (build_vector (i16 255), (i16 255))), (build_vector (i16 0), (i16 0)))),
- (v2i16 (smin (smax $src, (build_vector (i16 255), (i16 255))), (build_vector (i16 0), (i16 0))))
+ (v2i16 (smin (smax $src, (build_vector (i16 0), (i16 0))), (build_vector (i16 255), (i16 255))))
]
>;
diff --git a/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll b/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
index feb4bd73e39ba3..12001faff52ebc 100644
--- a/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
@@ -866,5 +866,81 @@ define i16 @basic_smax_smin_vec_input(<2 x i16> %src) {
%cast = bitcast <2 x i8> %vec.trunc to i16
ret i16 %cast
}
+define i16 @basic_smax_smin_vec_input_rev(<2 x i16> %src) {
+; SDAG-VI-LABEL: basic_smax_smin_vec_input_rev:
+; SDAG-VI: ; %bb.0:
+; SDAG-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-VI-NEXT: v_mov_b32_e32 v1, 0
+; SDAG-VI-NEXT: v_max_i16_sdwa v1, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; SDAG-VI-NEXT: v_max_i16_e32 v0, 0, v0
+; SDAG-VI-NEXT: v_mov_b32_e32 v2, 0xff
+; SDAG-VI-NEXT: v_min_i16_e32 v0, 0xff, v0
+; SDAG-VI-NEXT: v_min_i16_sdwa v1, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; SDAG-VI-NEXT: v_or_b32_e32 v0, v0, v1
+; SDAG-VI-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX9-LABEL: basic_smax_smin_vec_input_rev:
+; SDAG-GFX9: ; %bb.0:
+; SDAG-GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX9-NEXT: v_sat_pk_u8_i16_e32 v0, v0
+; SDAG-GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX11-LABEL: basic_smax_smin_vec_input_rev:
+; SDAG-GFX11: ; %bb.0:
+; SDAG-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX11-NEXT: v_pk_max_i16 v0, v0, 0
+; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; SDAG-GFX11-NEXT: v_pk_min_i16 v0, 0xff, v0 op_sel_hi:[0,1]
+; SDAG-GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; SDAG-GFX11-NEXT: v_lshlrev_b16 v1, 8, v1
+; SDAG-GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; SDAG-GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-VI-LABEL: basic_smax_smin_vec_input_rev:
+; GISEL-VI: ; %bb.0:
+; GISEL-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-VI-NEXT: v_mov_b32_e32 v2, 0
+; GISEL-VI-NEXT: v_max_i16_e32 v1, 0, v0
+; GISEL-VI-NEXT: v_max_i16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GISEL-VI-NEXT: v_mov_b32_e32 v2, 0xff
+; GISEL-VI-NEXT: v_min_i16_e32 v1, 0xff, v1
+; GISEL-VI-NEXT: v_min_i16_sdwa v0, v0, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GISEL-VI-NEXT: v_or_b32_e32 v0, v1, v0
+; GISEL-VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX9-LABEL: basic_smax_smin_vec_input_rev:
+; GISEL-GFX9: ; %bb.0:
+; GISEL-GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX9-NEXT: v_pk_max_i16 v0, 0, v0
+; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, 0xff00ff
+; GISEL-GFX9-NEXT: v_pk_min_i16 v0, v1, v0
+; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, 0xff
+; GISEL-GFX9-NEXT: v_and_b32_sdwa v1, v0, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GISEL-GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GISEL-GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX11-LABEL: basic_smax_smin_vec_input_rev:
+; GISEL-GFX11: ; %bb.0:
+; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX11-NEXT: v_pk_max_i16 v0, 0, v0
+; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GISEL-GFX11-NEXT: v_pk_min_i16 v0, 0xff00ff, v0
+; GISEL-GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GISEL-GFX11-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GISEL-GFX11-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GISEL-GFX11-NEXT: v_lshlrev_b16 v1, 8, v1
+; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; GISEL-GFX11-NEXT: s_setpc_b64 s[30:31]
+
+ %smax = call <2 x i16> @llvm.smax.v2i16(<2 x i16> <i16 0, i16 0>, <2 x i16> %src)
+ %smed = call <2 x i16> @llvm.smin.v2i16(<2 x i16> <i16 255, i16 255>, <2 x i16> %smax)
+ %vec.trunc = trunc <2 x i16> %smed to <2 x i8>
+ %cast = bitcast <2 x i8> %vec.trunc to i16
+ ret i16 %cast
+}
+
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GFX11: {{.*}}
>From f2614bbe69f8870943dc82b0b29791616d3e0211 Mon Sep 17 00:00:00 2001
From: shore <372660931 at qq.com>
Date: Fri, 27 Dec 2024 09:25:02 +0800
Subject: [PATCH 5/6] update main & add test
---
llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll | 68 ++++++++++++++++++++-
1 file changed, 67 insertions(+), 1 deletion(-)
diff --git a/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll b/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
index 12001faff52ebc..2ba7d04b82294e 100644
--- a/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
@@ -655,8 +655,74 @@ define i16 @basic_smax_smin_bit_or(i16 %src0, i16 %src1) {
%or = or i16 %src0.and, %src1.shl
ret i16 %or
}
+define i16 @basic_umax_umin_bit_or(i16 %src0, i16 %src1) {
+; SDAG-VI-LABEL: basic_umax_umin_bit_or:
+; SDAG-VI: ; %bb.0:
+; SDAG-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-VI-NEXT: v_mov_b32_e32 v2, 0xff
+; SDAG-VI-NEXT: v_min_u16_e32 v0, 0xff, v0
+; SDAG-VI-NEXT: v_min_u16_sdwa v1, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; SDAG-VI-NEXT: v_or_b32_e32 v0, v0, v1
+; SDAG-VI-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX9-LABEL: basic_umax_umin_bit_or:
+; SDAG-GFX9: ; %bb.0:
+; SDAG-GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX9-NEXT: s_movk_i32 s4, 0xff
+; SDAG-GFX9-NEXT: v_min_u16_e32 v0, 0xff, v0
+; SDAG-GFX9-NEXT: v_min_u16_sdwa v1, v1, s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; SDAG-GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; SDAG-GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; SDAG-GFX11-LABEL: basic_umax_umin_bit_or:
+; SDAG-GFX11: ; %bb.0:
+; SDAG-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX11-NEXT: v_min_u16 v1, 0xff, v1
+; SDAG-GFX11-NEXT: v_min_u16 v0, 0xff, v0
+; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; SDAG-GFX11-NEXT: v_lshlrev_b16 v1, 8, v1
+; SDAG-GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; SDAG-GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-VI-LABEL: basic_umax_umin_bit_or:
+; GISEL-VI: ; %bb.0:
+; GISEL-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-VI-NEXT: v_mov_b32_e32 v2, 0xff
+; GISEL-VI-NEXT: v_min_u16_e32 v0, 0xff, v0
+; GISEL-VI-NEXT: v_min_u16_sdwa v1, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GISEL-VI-NEXT: v_or_b32_e32 v0, v0, v1
+; GISEL-VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX9-LABEL: basic_umax_umin_bit_or:
+; GISEL-GFX9: ; %bb.0:
+; GISEL-GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX9-NEXT: v_mov_b32_e32 v2, 0xff
+; GISEL-GFX9-NEXT: v_min_u16_e32 v0, 0xff, v0
+; GISEL-GFX9-NEXT: v_min_u16_sdwa v1, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GISEL-GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GISEL-GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX11-LABEL: basic_umax_umin_bit_or:
+; GISEL-GFX11: ; %bb.0:
+; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX11-NEXT: v_min_u16 v1, 0xff, v1
+; GISEL-GFX11-NEXT: v_min_u16 v0, 0xff, v0
+; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GISEL-GFX11-NEXT: v_lshlrev_b16 v1, 8, v1
+; GISEL-GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; GISEL-GFX11-NEXT: s_setpc_b64 s[30:31]
+
+ %src0.max = call i16 @llvm.umax.i16(i16 %src0, i16 0)
+ %src0.clamp = call i16 @llvm.umin.i16(i16 %src0.max, i16 255)
+ %src1.max = call i16 @llvm.umax.i16(i16 %src1, i16 0)
+ %src1.clamp = call i16 @llvm.umin.i16(i16 %src1.max, i16 255)
+ %src0.and = and i16 %src0.clamp, 255
+ %src1.shl = shl i16 %src1.clamp, 8
+ %or = or i16 %src0.and, %src1.shl
+ ret i16 %or
+}
define i16 @basic_smax_smin_vec_cast(i16 %src0, i16 %src1) {
-;; SDAG-VI-LABEL: basic_smax_smin_vec_cast:
+; SDAG-VI-LABEL: basic_smax_smin_vec_cast:
; SDAG-VI: ; %bb.0:
; SDAG-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SDAG-VI-NEXT: v_max_i16_e32 v0, 0, v0
>From 53c3c3bbbf6dd0625cc976476bf480e2cab505a9 Mon Sep 17 00:00:00 2001
From: shore <372660931 at qq.com>
Date: Sat, 28 Dec 2024 20:44:04 +0800
Subject: [PATCH 6/6] fix globalisel, merge main
---
llvm/lib/Target/AMDGPU/AMDGPUInstructions.td | 12 +++++++++++-
llvm/lib/Target/AMDGPU/SIInstructions.td | 11 +++++++----
llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll | 14 ++------------
3 files changed, 20 insertions(+), 17 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
index 230c2fff5f3196..3e094de311d522 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
@@ -330,7 +330,7 @@ def conc_lo_u8_i16 : PatFrags<
(or
(and (i16 $src0), (i16 255)),
(shl (i16 $src1), (i16 8))
- ),
+ )
]
>;
@@ -351,6 +351,16 @@ def conc_lo_v2i16_i16 : PatFrags<
(i16 (trunc(srl (i32 (bitconvert $src)), (i32 16)))),
(i16 8)
)
+ ),
+ (or
+ (and (i16 (trunc (i32 (bitconvert $src)))), (i16 255)),
+ (shl
+ (and
+ (i16 (trunc (srl (i32 (bitconvert $src)), (i32 16)))),
+ (i16 255)
+ ),
+ (i16 8)
+ )
)
]
>;
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index 5e491e1fcea7ec..825395257f4f85 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -10,7 +10,10 @@
// that are not yet supported remain commented out.
//===----------------------------------------------------------------------===//
-class GCNPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl;
+class GCNPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl, GISelFlags;
+
+let GIIgnoreCopies = 1 in
+class GCNPatIgnoreCopies<dag pattern, dag result> : GCNPat<pattern, result>;
class UniformSextInreg<ValueType VT> : PatFrag<
(ops node:$src),
@@ -3299,21 +3302,21 @@ def : GCNPat <
>;
multiclass V_SAT_PK_Pat<Instruction inst> {
- def: GCNPat<
+ def: GCNPatIgnoreCopies<
(i16 (conc_lo_u8_i16 (clamp_s16_u8 i16:$lo), (clamp_s16_u8 i16:$hi))),
(inst
(V_LSHL_OR_B32_e64 VGPR_32:$hi, (S_MOV_B32 (i32 16)),
(V_AND_B32_e64 VGPR_32:$lo, (S_MOV_B32 (i32 0xFFFF)))))
>;
- def: GCNPat<
+ def: GCNPatIgnoreCopies<
(i16 (conc_lo_u8_i16 (clamp_s16_u8 i16:$lo), (smax i16:$hi, (i16 0)))),
(inst
(V_LSHL_OR_B32_e64 VGPR_32:$hi, (S_MOV_B32 (i32 16)),
(V_AND_B32_e64 VGPR_32:$lo, (S_MOV_B32 (i32 0xFFFF)))))
>;
- def: GCNPat<
+ def: GCNPatIgnoreCopies<
(i16 (conc_lo_v2i16_i16 (clamp_v2i16_u8 v2i16:$src))),
(inst VGPR_32:$src)
>;
diff --git a/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll b/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
index 2ba7d04b82294e..e454bfe420ffc8 100644
--- a/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
@@ -903,12 +903,7 @@ define i16 @basic_smax_smin_vec_input(<2 x i16> %src) {
; GISEL-GFX9-LABEL: basic_smax_smin_vec_input:
; GISEL-GFX9: ; %bb.0:
; GISEL-GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, 0xff00ff
-; GISEL-GFX9-NEXT: v_pk_min_i16 v0, v1, v0
-; GISEL-GFX9-NEXT: v_pk_max_i16 v0, 0, v0
-; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, 0xff
-; GISEL-GFX9-NEXT: v_and_b32_sdwa v1, v0, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GISEL-GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GISEL-GFX9-NEXT: v_sat_pk_u8_i16_e32 v0, v0
; GISEL-GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX11-LABEL: basic_smax_smin_vec_input:
@@ -978,12 +973,7 @@ define i16 @basic_smax_smin_vec_input_rev(<2 x i16> %src) {
; GISEL-GFX9-LABEL: basic_smax_smin_vec_input_rev:
; GISEL-GFX9: ; %bb.0:
; GISEL-GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX9-NEXT: v_pk_max_i16 v0, 0, v0
-; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, 0xff00ff
-; GISEL-GFX9-NEXT: v_pk_min_i16 v0, v1, v0
-; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, 0xff
-; GISEL-GFX9-NEXT: v_and_b32_sdwa v1, v0, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GISEL-GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GISEL-GFX9-NEXT: v_sat_pk_u8_i16_e32 v0, v0
; GISEL-GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX11-LABEL: basic_smax_smin_vec_input_rev:
More information about the llvm-commits
mailing list