[clang] [llvm] [RISCV] Add Qualcomm uC Xqciac (Load-Store Adress calculation) extension (PR #121037)

[Sam Elliott via llvm-commits]

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@@ -184,6 +191,37 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
 } // hasSideEffects = 0, mayLoad = 0, mayStore = 0
 } // Predicates = [HasVendorXqcia, IsRV32], DecoderNamespace = "Xqcia"
 
+let Predicates = [HasVendorXqciac, IsRV32], DecoderNamespace = "Xqciac" in {
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+  def QC_C_MULADDI : RVInst16CL<0b001, 0b10, (outs GPRC:$rd_wb),
+                               (ins GPRC:$rd, GPRC:$rs1, uimm5:$uimm),
+                               "qc.c.muladdi", "$rd, $rs1, $uimm"> {
+    let Constraints = "$rd = $rd_wb";
+    bits<5> uimm;
+
+    let Inst{12-10} = uimm{3-1};
+    let Inst{6} = uimm{0};
+    let Inst{5} = uimm{4};
+  }
----------------
lenary wrote:

@topperc there are other issues with adding compresspats for Xqci instructions which we are aware of and making plans to address - mostly around the fact there's no way to switch compresspats off for a pat where the larger and smaller instruction are in the same extension. We have a sketch of the solution internally but I've not finished it because we see CompressPats as an optimisation, not part of base assembler/linker support.

https://github.com/llvm/llvm-project/pull/121037