[llvm] [MachineScheduler] Remove TODO and replace computation with variable (PR #119551)

[via llvm-commits]

https://github.com/ywgrit updated https://github.com/llvm/llvm-project/pull/119551

>From 8cf73e9b4c4f11c8dbe031dc9bc7a2ed0f292f31 Mon Sep 17 00:00:00 2001
From: Xin Wang <yw987194828 at gmail.com>
Date: Wed, 11 Dec 2024 20:25:06 +0800
Subject: [PATCH] [MachineScheduler] Check whether the SU must end a dispatch
 group

Check whether the SU must end a dispatch group in VLIWMachineScheduler

Remove the remaining TODO checks as 3d594370933b515234c208a85a1c091d3e38d7f7
already checked whether the SU must be issued alone, i.e., instruction
that must be start/end a group. For example, in Cortex-R52 processor,
vector load/stores can issue only in slot-0 and dual-issue with
another instruction in slot-1, but only in the last issue. This
provides finer control over instruction scheduling based on the
design of each microarchitecture. In this way, the scheduler
models more accurately the real pipeline behavior.
---
 llvm/lib/CodeGen/MachineScheduler.cpp     | 5 +----
 llvm/lib/CodeGen/VLIWMachineScheduler.cpp | 4 +++-
 2 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index 1722bdda99e4af..3319ccfc30a9be 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -2450,8 +2450,6 @@ SchedBoundary::getNextResourceCycle(const MCSchedClassDesc *SC, unsigned PIdx,
 /// simple counters that the scheduler itself maintains. It explicitly checks
 /// for instruction dispatch limitations, including the number of micro-ops that
 /// can dispatch per cycle.
-///
-/// TODO: Also check whether the SU must start a new group.
 bool SchedBoundary::checkHazard(SUnit *SU) {
   if (HazardRec->isEnabled()
       && HazardRec->getHazardType(SU) != ScheduleHazardRecognizer::NoHazard) {
@@ -2460,8 +2458,7 @@ bool SchedBoundary::checkHazard(SUnit *SU) {
 
   unsigned uops = SchedModel->getNumMicroOps(SU->getInstr());
   if ((CurrMOps > 0) && (CurrMOps + uops > SchedModel->getIssueWidth())) {
-    LLVM_DEBUG(dbgs() << "  SU(" << SU->NodeNum << ") uops="
-                      << SchedModel->getNumMicroOps(SU->getInstr()) << '\n');
+    LLVM_DEBUG(dbgs() << "  SU(" << SU->NodeNum << ") uops=" << uops << '\n');
     return true;
   }
 
diff --git a/llvm/lib/CodeGen/VLIWMachineScheduler.cpp b/llvm/lib/CodeGen/VLIWMachineScheduler.cpp
index 0cddf59d0ca2ac..531d50c73444df 100644
--- a/llvm/lib/CodeGen/VLIWMachineScheduler.cpp
+++ b/llvm/lib/CodeGen/VLIWMachineScheduler.cpp
@@ -428,7 +428,9 @@ void ConvergingVLIWScheduler::VLIWSchedBoundary::bumpNode(SUnit *SU) {
   startNewCycle = ResourceModel->reserveResources(SU, isTop());
 
   // Check the instruction group dispatch limit.
-  // TODO: Check if this SU must end a dispatch group.
+  assert(IssueCount == 0 ||
+         (!(isTop() && SchedModel->mustBeginGroup(SU->getInstr())) &&
+          !(!isTop() && SchedModel->mustEndGroup(SU->getInstr()))));
   IssueCount += SchedModel->getNumMicroOps(SU->getInstr());
   if (startNewCycle) {
     LLVM_DEBUG(dbgs() << "*** Max instrs at cycle " << CurrCycle << '\n');