[llvm] Add SD matchers and unit test coverage for ISD::VECTOR_SHUFFLE (PR #119592)

[Min-Yih Hsu via llvm-commits]

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@@ -133,13 +134,11 @@ TEST_F(SelectionDAGPatternMatchTest, matchVecShuffle) {
       DAG->getVectorShuffle(VInt32VT, DL, V0, V1, MaskData);
 
   using namespace SDPatternMatch;
+  EXPECT_TRUE(sd_match(VecShuffleWithMask, m_Shuffle(m_Value(), m_Value())));
   EXPECT_TRUE(sd_match(VecShuffleWithMask,
-                       m_Shuffle(m_Value(), m_Value(), CapturedMask)));
+                       m_Shuffle(m_Value(), m_Value(), m_Mask(CapturedMask))));
   EXPECT_TRUE(sd_match(VecShuffleWithMask,
-                       m_ShuffleSpecificMask(m_Value(), m_Value(), MaskData)));
-  EXPECT_FALSE(
-      sd_match(VecShuffleWithMask,
-               m_ShuffleSpecificMask(m_Value(), m_Value(), OtherMaskData)));
+                       m_Shuffle(m_Value(), m_Value(), m_SpecificMask(Mask))));
   EXPECT_TRUE(std::equal(MaskData.begin(), MaskData.end(), CapturedMask.begin(),
                          CapturedMask.end()));
   EXPECT_FALSE(std::equal(OtherMaskData.begin(), OtherMaskData.end(),
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mshockwave wrote:

> It is tested for equality with the test above MaskData==CaptureMask, but in the case of an empty mask or an incorrect equality comparison (as I mistakenly implemented before) should we keep it around?

The `std::equal(ItBegin1, ItEnd1, ItBegin2, ItEnd2)` checks if both iterator ranges have the same length first, so if one is empty and the other is not we should be able to catch it (You were previously using the `std::equal(ItBegin1, ItEnd1, ItBegin2)` variant which doesn't check the length, hence yielding false positive in the presence of empty mask).

Therefore, with this reason and the fact that we have checked `MaskData==CaptureMask`, that's why I think having a negative test of `CaptureMask==OtherMaskData` is less meaningful.

https://github.com/llvm/llvm-project/pull/119592