[llvm] [RISCV] Add a generic OoO CPU (PR #120712)

[Craig Topper via llvm-commits]

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@@ -0,0 +1,287 @@
+//===-- RISCVSchedGenericOOO.td - Generic O3 Processor -----*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// We assume that:
+// * 6-issue out-of-order CPU with 128 ROB entries.
+// * Units:
+//   * IXU (Integer GenericOOOALU Unit): 4 units, only one can execute division.
+//   * FXU (Floating-point Unit): 2 units.
+//   * LSU (Load/Store Unit): 2 units.
+//   * VXU (Vector Unit): 1 unit.
+// * Latency:
+//   * Integer instructions: 1 cycle.
+//   * Multiplication instructions: 4 cycles.
+//   * Multiplication/Division instructions: 7-13 cycles.
+//   * Floating-point instructions: 4-6 cycles.
+//   * Vector instructions: 2-6 cycles.
+//   * Load/Store:
+//     * IXU: 4 cycles.
+//     * FXU: 6 cycles.
+//     * VXU: 6 cycles.
+// * Integer/floating-point/vector div/rem/sqrt/... are non-pipelined.
+// * 
+//===----------------------------------------------------------------------===//
+
+def GenericOOOModel : SchedMachineModel {
+  int IssueWidth = 6;
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topperc wrote:

Why did we go to 6? I thought 4 was reasonable.

https://github.com/llvm/llvm-project/pull/120712