[llvm] [AArch64] Prefer SVE2.2 zeroing forms of certain instructions with an all-true predicate (PR #120595)

[Momchil Velikov via llvm-commits]

momchil-velikov wrote:

> I was pretty sure this would conflict with #118788, but apparently not.

Right, neither of these patches touches `FCVTXNT`, `FCVTNT`, or `BFCVTNT`. It's not entirely clear when do we want to generate the zeroing forms of these instructions, and we don't have yet "zeroing" intrinsics defined.


https://github.com/llvm/llvm-project/pull/120595