[llvm] [TableGen][GISel] Learn to import patterns with physreg defs (PR #120343)

Sergei Barannikov via llvm-commits llvm-commits at lists.llvm.org
Sun Dec 22 23:50:10 PST 2024


s-barannikov wrote:

> I'd expect an arbitrary copy from a physical register to be copied to/from a virtual register with class getMinimalPhysRegClass (or whatever the equivalent is in CodeGenRegisters. getRegClassForRegister?).

That's what I thought, too. It appears that `getMinimalPhysRegClass` may return an unallocatable register class and we aren't allowed to create virtual registers with unallocatable classes. This is the case on my target and I believe ARM would suffer from this too as its "condition codes" register class is unallocatable as well. `getRegClassForRegister` looks better, but it falls under category "some arbitrary register class".

In SelectionDAG, the choice of the class is done by InstrEmitter, and the logic is rather [complicated](https://github.com/llvm/llvm-project/blob/104ad9258a0f93a969bf7a85ebc0c7d9c533edf1/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp#L101). In the simplest case it just calls `TLI->getRegClassFor()`, which returns the class registered by a call to `addRegisterClass()` in target's `TargetLowering` constructor.  At TableGen level, we don't know what register classes are going to be legal for a value type, so we probably need to emit something to do a runtime check. Maybe something like `GIR_Constrain[PhysReg]Copy` that would call a target hook?

> ConstrainSelectedInstOperands won't work because that just uses the classes from the instruction definition, where generic pseudos like COPY do not have any available register class information. These need manual selection

I had to figure it out the hard way :(


https://github.com/llvm/llvm-project/pull/120343


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