[llvm] d325099 - [RISCV] Rewrite an isel pattern to make it more amenable to GISel. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2024-12-22T13:31:33-08:00
New Revision: d32509928ba6b4c78b02b8a8499dce056ae6fe52

URL: https://github.com/llvm/llvm-project/commit/d32509928ba6b4c78b02b8a8499dce056ae6fe52
DIFF: https://github.com/llvm/llvm-project/commit/d32509928ba6b4c78b02b8a8499dce056ae6fe52.diff

LOG: [RISCV] Rewrite an isel pattern to make it more amenable to GISel. NFC

The result pattern created an i1 constant and then used
ImmSubFromXLen SDNodeXForm on it. GISel cannot handle this construct
the same way as SelectionDAG. The GISel equivalent of the SDNodeXForm
expects a G_CONSTANT, but the emitter can't create that.

Work aound this by splitting the pattern into RV32 and RV64 versions
and hard coding the constant.

Additional changes are needed to import the pattern for GISel so
there's no test.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfo.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index af3ab88f700bff..3cb8a2dae5470f 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1348,9 +1348,10 @@ def add_like : PatFrags<(ops node:$lhs, node:$rhs),
 
 // negate of low bit can be done via two (compressible) shifts.  The negate
 // is never compressible since rs1 and rd can't be the same register.
-def : Pat<(XLenVT (sub 0, (and_oneuse GPR:$rs, 1))),
-          (SRAI (XLenVT (SLLI $rs, (ImmSubFromXLen (XLenVT 1)))),
-                (ImmSubFromXLen (XLenVT 1)))>;
+def : Pat<(i32 (sub 0, (and_oneuse GPR:$rs, 1))),
+          (SRAI (i32 (SLLI $rs, 31)), 31)>, Requires<[IsRV32]>;
+def : Pat<(i64 (sub 0, (and_oneuse GPR:$rs, 1))),
+          (SRAI (i64 (SLLI $rs, 63)), 63)>, Requires<[IsRV64]>;
 
 // AND with leading/trailing ones mask exceeding simm32/simm12.
 def : Pat<(i64 (and GPR:$rs, immop_oneuse<LeadingOnesMask>:$mask)),