[llvm] [RISCV] Pattern-match frameindex (NFCI) (PR #120917)
Sergei Barannikov via llvm-commits
llvm-commits at lists.llvm.org
Sun Dec 22 12:25:10 PST 2024
https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/120917
>From a54b8796b2598e013cdf662a7e5e8f952d902795 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov <barannikov88 at gmail.com>
Date: Sun, 22 Dec 2024 23:05:35 +0300
Subject: [PATCH] [RISCV] Pattern-match frameindex (NFCI)
---
llvm/include/llvm/Target/GenericOpcodes.td | 2 +-
.../RISCV/GISel/RISCVInstructionSelector.cpp | 18 ++++++++-------
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 23 -------------------
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h | 1 -
llvm/lib/Target/RISCV/RISCVInstrInfo.td | 18 +++++++++++----
5 files changed, 24 insertions(+), 38 deletions(-)
diff --git a/llvm/include/llvm/Target/GenericOpcodes.td b/llvm/include/llvm/Target/GenericOpcodes.td
index c8f91cd0de5978..e134bab61bf63c 100644
--- a/llvm/include/llvm/Target/GenericOpcodes.td
+++ b/llvm/include/llvm/Target/GenericOpcodes.td
@@ -99,7 +99,7 @@ def G_PHI : GenericInstruction {
}
def G_FRAME_INDEX : GenericInstruction {
- let OutOperandList = (outs type0:$dst);
+ let OutOperandList = (outs ptype0:$dst);
let InOperandList = (ins unknown:$src2);
let hasSideEffects = false;
}
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 5aa66b3780b86b..ef85057ba1264d 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -131,6 +131,8 @@ class RISCVInstructionSelector : public InstructionSelector {
int OpIdx) const;
void renderImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
int OpIdx) const;
+ void renderFrameIndex(MachineInstrBuilder &MIB, const MachineInstr &MI,
+ int OpIdx) const;
void renderTrailingZeros(MachineInstrBuilder &MIB, const MachineInstr &MI,
int OpIdx) const;
@@ -715,14 +717,6 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
MI.setDesc(TII.get(RISCV::PseudoBRIND));
MI.addOperand(MachineOperand::CreateImm(0));
return constrainSelectedInstRegOperands(MI, TII, TRI, RBI);
- case TargetOpcode::G_FRAME_INDEX: {
- // TODO: We may want to replace this code with the SelectionDAG patterns,
- // which fail to get imported because it uses FrameAddrRegImm, which is a
- // ComplexPattern
- MI.setDesc(TII.get(RISCV::ADDI));
- MI.addOperand(MachineOperand::CreateImm(0));
- return constrainSelectedInstRegOperands(MI, TII, TRI, RBI);
- }
case TargetOpcode::G_SELECT:
return selectSelect(MI, MIB);
case TargetOpcode::G_FCMP:
@@ -859,6 +853,14 @@ void RISCVInstructionSelector::renderImm(MachineInstrBuilder &MIB,
MIB.addImm(CstVal);
}
+void RISCVInstructionSelector::renderFrameIndex(MachineInstrBuilder &MIB,
+ const MachineInstr &MI,
+ int OpIdx) const {
+ assert(MI.getOpcode() == TargetOpcode::G_FRAME_INDEX && OpIdx == -1 &&
+ "Expected G_FRAME_INDEX");
+ MIB.add(MI.getOperand(1));
+}
+
void RISCVInstructionSelector::renderTrailingZeros(MachineInstrBuilder &MIB,
const MachineInstr &MI,
int OpIdx) const {
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index b33d58d177457e..0070fd4520429f 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -2531,29 +2531,6 @@ bool RISCVDAGToDAGISel::SelectAddrFrameIndex(SDValue Addr, SDValue &Base,
return false;
}
-// Select a frame index and an optional immediate offset from an ADD or OR.
-bool RISCVDAGToDAGISel::SelectFrameAddrRegImm(SDValue Addr, SDValue &Base,
- SDValue &Offset) {
- if (SelectAddrFrameIndex(Addr, Base, Offset))
- return true;
-
- if (!CurDAG->isBaseWithConstantOffset(Addr))
- return false;
-
- if (auto *FIN = dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
- int64_t CVal = cast<ConstantSDNode>(Addr.getOperand(1))->getSExtValue();
- if (isInt<12>(CVal)) {
- Base = CurDAG->getTargetFrameIndex(FIN->getIndex(),
- Subtarget->getXLenVT());
- Offset = CurDAG->getSignedTargetConstant(CVal, SDLoc(Addr),
- Subtarget->getXLenVT());
- return true;
- }
- }
-
- return false;
-}
-
// Fold constant addresses.
static bool selectConstantAddr(SelectionDAG *CurDAG, const SDLoc &DL,
const MVT VT, const RISCVSubtarget *Subtarget,
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
index e75aff7eda9938..592f517358506b 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
@@ -46,7 +46,6 @@ class RISCVDAGToDAGISel : public SelectionDAGISel {
std::vector<SDValue> &OutOps) override;
bool SelectAddrFrameIndex(SDValue Addr, SDValue &Base, SDValue &Offset);
- bool SelectFrameAddrRegImm(SDValue Addr, SDValue &Base, SDValue &Offset);
bool SelectAddrRegImm(SDValue Addr, SDValue &Base, SDValue &Offset,
bool IsRV32Zdinx = false);
bool SelectAddrRegImmRV32Zdinx(SDValue Addr, SDValue &Base, SDValue &Offset) {
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index af3ab88f700bff..1750bdd7e15038 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -400,9 +400,6 @@ def uimm6gt32 : ImmLeaf<XLenVT, [{
}]>;
// Addressing modes.
-// Necessary because a frameindex can't be matched directly in a pattern.
-def FrameAddrRegImm : ComplexPattern<iPTR, 2, "SelectFrameAddrRegImm",
- [frameindex, or, add]>;
def AddrRegImm : ComplexPattern<iPTR, 2, "SelectAddrRegImm">;
// Return the negation of an immediate value.
@@ -1400,8 +1397,19 @@ def PseudoAddTPRel : Pseudo<(outs GPR:$rd),
/// FrameIndex calculations
-def : Pat<(FrameAddrRegImm (iPTR GPR:$rs1), simm12:$imm12),
- (ADDI GPR:$rs1, simm12:$imm12)>;
+// Transforms frameindex -> tframeindex.
+def to_tframeindex : SDNodeXForm<frameindex, [{
+ return CurDAG->getTargetFrameIndex(N->getIndex(), N->getValueType(0));
+}]>;
+
+def : GICustomOperandRenderer<"renderFrameIndex">,
+ GISDNodeXFormEquiv<to_tframeindex>;
+
+def : Pat<(frameindex:$fi), (ADDI (iPTR (to_tframeindex $fi)), 0)>;
+
+def : Pat<(add_like frameindex:$fi, simm12:$offset),
+ (ADDI (iPTR (to_tframeindex $fi)), simm12:$offset)>;
+
def GIAddrRegImm :
GIComplexOperandMatcher<s32, "selectAddrRegImm">,
GIComplexPatternEquiv<AddrRegImm>;
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