[llvm] [TableGen][GlobalISel] Add GINodeEquiv for sdivrem/udivrem (PR #120819)

Sergei Barannikov via llvm-commits llvm-commits at lists.llvm.org
Fri Dec 20 19:34:59 PST 2024


https://github.com/s-barannikov created https://github.com/llvm/llvm-project/pull/120819

These nodes are not currently used in DAG patterns. Their GlobalISel equivalents are primarily useful for testing TableGen backend, as they produce two results. (There doesn't seem to be other such nodes.)

>From 072bc715a5918b07ce8e63abeb3d238d40cc6a75 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov <barannikov88 at gmail.com>
Date: Sat, 21 Dec 2024 06:29:47 +0300
Subject: [PATCH] [TableGen][GlobalISel] Add GINodeEquiv for sdivrem/udivrem

These nodes are not currently used in DAG patterns. Their GlobalISel
equivalents are primarily useful for testing TableGen backend, as they
produce two results. (There doesn't seem to be other such nodes.)
---
 llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td | 2 ++
 llvm/include/llvm/Target/TargetSelectionDAG.td            | 4 ++--
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
index 2148f5be4c41aa..c8c0eeb57099a2 100644
--- a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
+++ b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
@@ -70,6 +70,8 @@ def : GINodeEquiv<G_SDIV, sdiv>;
 def : GINodeEquiv<G_UDIV, udiv>;
 def : GINodeEquiv<G_SREM, srem>;
 def : GINodeEquiv<G_UREM, urem>;
+def : GINodeEquiv<G_SDIVREM, sdivrem>;
+def : GINodeEquiv<G_UDIVREM, udivrem>;
 def : GINodeEquiv<G_AND, and>;
 def : GINodeEquiv<G_OR, or>;
 def : GINodeEquiv<G_XOR, xor>;
diff --git a/llvm/include/llvm/Target/TargetSelectionDAG.td b/llvm/include/llvm/Target/TargetSelectionDAG.td
index 2c58eedce1de0b..bee0a4298c786f 100644
--- a/llvm/include/llvm/Target/TargetSelectionDAG.td
+++ b/llvm/include/llvm/Target/TargetSelectionDAG.td
@@ -128,8 +128,8 @@ def SDTIntShiftDOp: SDTypeProfile<1, 3, [   // fshl, fshr
 def SDTIntSatNoShOp : SDTypeProfile<1, 2, [   // ssat with no shift
   SDTCisSameAs<0, 1>, SDTCisInt<2>
 ]>;
-def SDTIntBinHiLoOp : SDTypeProfile<2, 2, [ // mulhi, mullo, sdivrem, udivrem
-  SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,SDTCisInt<0>
+def SDTIntBinHiLoOp : SDTypeProfile<2, 2, [ // smullohi, umullohi, sdivrem, udivrem
+  SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisInt<0>
 ]>;
 def SDTIntScaledBinOp : SDTypeProfile<1, 3, [  // smulfix, sdivfix, etc
   SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisInt<3>



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