[llvm] [RISCV] Intrinsic Support for XCVsimd (PR #118557)

[Craig Topper via llvm-commits]

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@@ -19066,6 +19066,24 @@ static MachineBasicBlock *emitFROUND(MachineInstr &MI, MachineBasicBlock *MBB,
   return DoneMBB;
 }
 
+static MachineBasicBlock *
+emitCV_SHUFFLE_SCI_B(MachineInstr &MI, MachineBasicBlock *MBB,
+                     const RISCVSubtarget &Subtarget) {
+  DebugLoc DL = MI.getDebugLoc();
+  Register DstReg = MI.getOperand(0).getReg();
+  Register SrcReg = MI.getOperand(1).getReg();
+  uint8_t Imm = MI.getOperand(2).getImm();
+  const unsigned Opcodes[] = {
+      RISCV::CV_SHUFFLEI0_SCI_B, RISCV::CV_SHUFFLEI1_SCI_B,
+      RISCV::CV_SHUFFLEI2_SCI_B, RISCV::CV_SHUFFLEI3_SCI_B};
+  const RISCVInstrInfo &TII = *Subtarget.getInstrInfo();
+  BuildMI(*MBB, MI, DL, TII.get(Opcodes[Imm >> 6]), DstReg)
+      .addReg(SrcReg)
+      .addImm(APInt(6, Imm, true).getSExtValue());
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topperc wrote:

Why sext? And there no tests that show it is sign extended.

You can use `signExtend64<6>(Imm)` instead of APInt.

https://github.com/llvm/llvm-project/pull/118557