[clang] [llvm] [Hexagon] Add V75 support to compiler and assembler (PR #120773)

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git-clang-format --diff 7739380643718bc912bc05b969e4be525a85c0d2 1d3ac02da5bfb00d86b123334e3a75628e47ef42 --extensions h,c,cpp -- clang/lib/Basic/Targets/Hexagon.cpp clang/test/Driver/hexagon-toolchain-elf.c clang/test/Misc/target-invalid-cpu-note/hexagon.c clang/test/Preprocessor/hexagon-predefines.c llvm/include/llvm/BinaryFormat/ELF.h llvm/lib/Object/ELFObjectFile.cpp llvm/lib/ObjectYAML/ELFYAML.cpp llvm/lib/Target/Hexagon/HexagonDepArch.h llvm/lib/Target/Hexagon/HexagonSubtarget.h llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/clang/lib/Basic/Targets/Hexagon.cpp b/clang/lib/Basic/Targets/Hexagon.cpp
index 1fce0d0ed0..931327bd86 100644
--- a/clang/lib/Basic/Targets/Hexagon.cpp
+++ b/clang/lib/Basic/Targets/Hexagon.cpp
@@ -232,13 +232,13 @@ struct CPUSuffix {
 };
 
 static constexpr CPUSuffix Suffixes[] = {
-    {{"hexagonv5"},  {"5"}},  {{"hexagonv55"},  {"55"}},
-    {{"hexagonv60"}, {"60"}}, {{"hexagonv62"},  {"62"}},
-    {{"hexagonv65"}, {"65"}}, {{"hexagonv66"},  {"66"}},
+    {{"hexagonv5"}, {"5"}},   {{"hexagonv55"}, {"55"}},
+    {{"hexagonv60"}, {"60"}}, {{"hexagonv62"}, {"62"}},
+    {{"hexagonv65"}, {"65"}}, {{"hexagonv66"}, {"66"}},
     {{"hexagonv67"}, {"67"}}, {{"hexagonv67t"}, {"67t"}},
-    {{"hexagonv68"}, {"68"}}, {{"hexagonv69"},  {"69"}},
+    {{"hexagonv68"}, {"68"}}, {{"hexagonv69"}, {"69"}},
     {{"hexagonv71"}, {"71"}}, {{"hexagonv71t"}, {"71t"}},
-    {{"hexagonv73"}, {"73"}}, {{"hexagonv75"},  {"75"}},
+    {{"hexagonv73"}, {"73"}}, {{"hexagonv75"}, {"75"}},
 };
 
 std::optional<unsigned> HexagonTargetInfo::getHexagonCPURev(StringRef Name) {
diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
index 40d2b122d4..dfa1f5471a 100644
--- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
+++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
@@ -453,18 +453,18 @@ std::string selectHexagonFS(StringRef CPU, StringRef FS) {
     break;
   case Hexagon::ArchEnum::Generic: {
     Result.push_back(StringSwitch<StringRef>(CPU)
-             .Case("hexagonv60", "+hvxv60")
-             .Case("hexagonv62", "+hvxv62")
-             .Case("hexagonv65", "+hvxv65")
-             .Case("hexagonv66", "+hvxv66")
-             .Case("hexagonv67", "+hvxv67")
-             .Case("hexagonv67t", "+hvxv67")
-             .Case("hexagonv68", "+hvxv68")
-             .Case("hexagonv69", "+hvxv69")
-             .Case("hexagonv71", "+hvxv71")
-             .Case("hexagonv71t", "+hvxv71")
-             .Case("hexagonv73", "+hvxv73")
-             .Case("hexagonv75", "+hvxv75"));
+                         .Case("hexagonv60", "+hvxv60")
+                         .Case("hexagonv62", "+hvxv62")
+                         .Case("hexagonv65", "+hvxv65")
+                         .Case("hexagonv66", "+hvxv66")
+                         .Case("hexagonv67", "+hvxv67")
+                         .Case("hexagonv67t", "+hvxv67")
+                         .Case("hexagonv68", "+hvxv68")
+                         .Case("hexagonv69", "+hvxv69")
+                         .Case("hexagonv71", "+hvxv71")
+                         .Case("hexagonv71t", "+hvxv71")
+                         .Case("hexagonv73", "+hvxv73")
+                         .Case("hexagonv75", "+hvxv75"));
     break;
   }
   case Hexagon::ArchEnum::NoArch:
@@ -512,8 +512,8 @@ FeatureBitset Hexagon_MC::completeHVXFeatures(const FeatureBitset &S) {
   // turns on hvxvNN, corresponding to the existing ArchVNN.
   FeatureBitset FB = S;
   unsigned CpuArch = ArchV5;
-  for (unsigned F : {ArchV75, ArchV73, ArchV71, ArchV69, ArchV68, ArchV67, ArchV66,
-                     ArchV65, ArchV62, ArchV60, ArchV55, ArchV5}) {
+  for (unsigned F : {ArchV75, ArchV73, ArchV71, ArchV69, ArchV68, ArchV67,
+                     ArchV66, ArchV65, ArchV62, ArchV60, ArchV55, ArchV5}) {
     if (!FB.test(F))
       continue;
     CpuArch = F;
@@ -527,9 +527,10 @@ FeatureBitset Hexagon_MC::completeHVXFeatures(const FeatureBitset &S) {
     break;
   }
   bool HasHvxVer = false;
-  for (unsigned F : {ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65,
-                     ExtensionHVXV66, ExtensionHVXV67, ExtensionHVXV68,
-        ExtensionHVXV69, ExtensionHVXV71, ExtensionHVXV73, ExtensionHVXV75}) {
+  for (unsigned F :
+       {ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65, ExtensionHVXV66,
+        ExtensionHVXV67, ExtensionHVXV68, ExtensionHVXV69, ExtensionHVXV71,
+        ExtensionHVXV73, ExtensionHVXV75}) {
     if (!FB.test(F))
       continue;
     HasHvxVer = true;

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https://github.com/llvm/llvm-project/pull/120773