[llvm] [RISCV] Add a generic OoO CPU (PR #120712)

[Craig Topper via llvm-commits]

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@@ -0,0 +1,272 @@
+//===-- RISCVSchedGenericOOO.td - Generic O3 Processor -----*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// We assume that:
+// * 8-issue out-of-order CPU with 128 ROB entries.
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topperc wrote:

8 issue feels high.

https://github.com/llvm/llvm-project/pull/120712