[llvm] [NFC][AArch64][SVE] Rename variables in partial reduction lowering functions (PR #120589)

via llvm-commits llvm-commits at lists.llvm.org
Fri Dec 20 02:09:37 PST 2024


github-actions[bot] wrote:

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git-clang-format --diff 411df3bb4941318a02a59b4cd7a898d4f9b788a3 8389aa3a6f758ab8c5cb9b4da1d94b095d5eac5e --extensions cpp -- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index b7c4845d39..f5a316d1d8 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -21838,7 +21838,8 @@ SDValue tryLowerPartialReductionToWideAdd(SDNode *N,
     return SDValue();
 
   bool ExtOpIsSigned = Ext.getOpcode() == ISD::SIGN_EXTEND;
-  unsigned BottomOpcode = ExtOpIsSigned ? AArch64ISD::SADDWB : AArch64ISD::UADDWB;
+  unsigned BottomOpcode =
+      ExtOpIsSigned ? AArch64ISD::SADDWB : AArch64ISD::UADDWB;
   unsigned TopOpcode = ExtOpIsSigned ? AArch64ISD::SADDWT : AArch64ISD::UADDWT;
   SDValue BottomNode = DAG.getNode(BottomOpcode, DL, AccVT, Acc, ExtOp);
   return DAG.getNode(TopOpcode, DL, AccVT, BottomNode, ExtOp);

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https://github.com/llvm/llvm-project/pull/120589


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