[llvm] [RISCV] Implement RISCVTTIImpl::getPreferredAddressingMode for HasVendorXCVmem (PR #120533)
Philipp van Kempen via llvm-commits
llvm-commits at lists.llvm.org
Fri Dec 20 02:07:47 PST 2024
https://github.com/PhilippvK updated https://github.com/llvm/llvm-project/pull/120533
>From 0cc75221d8c79c24950f3ef6b798f92cb9c615bb Mon Sep 17 00:00:00 2001
From: Philipp van Kempen <philipp.van-kempen at tum.de>
Date: Thu, 19 Dec 2024 08:21:08 +0100
Subject: [PATCH 1/4] [RISCV] Implement
RISCVTTIImpl::getPreferredAddressingMode for HasVendorXCVmem
For a simple matmult kernel this heuristic reduces the length of the critical basic
block from 15 to 20 instructions, resulting in a 20% speedup.
---
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp | 9 +++++++++
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h | 3 +++
2 files changed, 12 insertions(+)
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index 49192bd6380223..662649b5b276b1 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -2329,6 +2329,15 @@ unsigned RISCVTTIImpl::getMaximumVF(unsigned ElemWidth, unsigned Opcode) const {
return std::max<unsigned>(1U, RegWidth.getFixedValue() / ElemWidth);
}
+TTI::AddressingModeKind
+RISCVTTIImpl::getPreferredAddressingMode(const Loop *L,
+ ScalarEvolution *SE) const {
+ if (ST->hasVendorXCVmem())
+ return TTI::AMK_PostIndexed;
+
+ return TTI::AMK_None;
+}
+
bool RISCVTTIImpl::isLSRCostLess(const TargetTransformInfo::LSRCost &C1,
const TargetTransformInfo::LSRCost &C2) {
// RISC-V specific here are "instruction number 1st priority".
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
index bd90bfed6e2c95..9b364391f0fa47 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
@@ -388,6 +388,9 @@ class RISCVTTIImpl : public BasicTTIImplBase<RISCVTTIImpl> {
llvm_unreachable("unknown register class");
}
+ TTI::AddressingModeKind getPreferredAddressingMode(const Loop *L,
+ ScalarEvolution *SE) const;
+
unsigned getRegisterClassForType(bool Vector, Type *Ty = nullptr) const {
if (Vector)
return RISCVRegisterClass::VRRC;
>From 19b404cdf581c015dad48172d9f7000ab34dc929 Mon Sep 17 00:00:00 2001
From: Philipp van Kempen <philipp.van-kempen at tum.de>
Date: Thu, 19 Dec 2024 15:27:27 +0100
Subject: [PATCH 2/4] [RISCV] Address PR comment
---
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index 662649b5b276b1..b6e13fa7a90094 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -2335,7 +2335,7 @@ RISCVTTIImpl::getPreferredAddressingMode(const Loop *L,
if (ST->hasVendorXCVmem())
return TTI::AMK_PostIndexed;
- return TTI::AMK_None;
+ return BasicTTIImplBase::getPreferredAddressingMode(L, SE);
}
bool RISCVTTIImpl::isLSRCostLess(const TargetTransformInfo::LSRCost &C1,
>From 68527e1f8d38fa379a7bae6c9e32a774c03f9ed1 Mon Sep 17 00:00:00 2001
From: Philipp van Kempen <philipp.van-kempen at tum.de>
Date: Fri, 20 Dec 2024 11:06:21 +0100
Subject: [PATCH 3/4] [RISCV] add !ST->is64Bit() check
---
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index b6e13fa7a90094..2f9beb0b3983c5 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -2332,7 +2332,7 @@ unsigned RISCVTTIImpl::getMaximumVF(unsigned ElemWidth, unsigned Opcode) const {
TTI::AddressingModeKind
RISCVTTIImpl::getPreferredAddressingMode(const Loop *L,
ScalarEvolution *SE) const {
- if (ST->hasVendorXCVmem())
+ if (ST->hasVendorXCVmem() && !ST->is64Bit())
return TTI::AMK_PostIndexed;
return BasicTTIImplBase::getPreferredAddressingMode(L, SE);
>From b6e772232217dcd685d8931b37aed103ce7bda18 Mon Sep 17 00:00:00 2001
From: Philipp van Kempen <philipp.van-kempen at tum.de>
Date: Fri, 20 Dec 2024 11:07:06 +0100
Subject: [PATCH 4/4] [RISCV] add test case for XCVmem addressing mode
heuristic
---
llvm/test/CodeGen/RISCV/xcvmem-heuristic.ll | 34 +++++++++++++++++++++
1 file changed, 34 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/xcvmem-heuristic.ll
diff --git a/llvm/test/CodeGen/RISCV/xcvmem-heuristic.ll b/llvm/test/CodeGen/RISCV/xcvmem-heuristic.ll
new file mode 100644
index 00000000000000..c8832bf49dd6a2
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/xcvmem-heuristic.ll
@@ -0,0 +1,34 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -O3 -mtriple=riscv32 -mattr=+m,+xcvmem -verify-machineinstrs < %s \
+; RUN: | FileCheck %s --check-prefixes=CHECK
+
+define i32 @test_heuristic(ptr %b, i32 %e, i1 %0) {
+; CHECK-LABEL: test_heuristic:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: add a3, a0, a1
+; CHECK-NEXT: andi a2, a2, 1
+; CHECK-NEXT: .LBB0_1: # %loop
+; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: cv.lbu a1, (a3), 1
+; CHECK-NEXT: addi a0, a0, 1
+; CHECK-NEXT: beqz a2, .LBB0_1
+; CHECK-NEXT: # %bb.2: # %exit
+; CHECK-NEXT: mv a0, a1
+; CHECK-NEXT: ret
+entry:
+ %1 = getelementptr i8, ptr %b, i32 %e
+ br label %loop
+
+loop: ; preds = %loop, %entry
+ %2 = phi ptr [ %b, %entry ], [ %7, %loop ]
+ %3 = phi ptr [ %1, %entry ], [ %8, %loop ]
+ %4 = load i8, ptr %2, align 1
+ %5 = load i8, ptr %3, align 1
+ %6 = zext i8 %5 to i32
+ %7 = getelementptr i8, ptr %2, i32 1
+ %8 = getelementptr i8, ptr %3, i32 1
+ br i1 %0, label %exit, label %loop
+
+exit: ; preds = %loop
+ ret i32 %6
+}
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