[llvm] [AMDGPU] Supporting dynamically sized allocas (PR #120705)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Dec 20 01:56:06 PST 2024
https://github.com/easyonaadit created https://github.com/llvm/llvm-project/pull/120705
When the stack space to be allocated is not known at
compile time, a wave wide reduction is applied to get
the maximum stack size needed.
Uniform stack pointer is updated accordingly.
>From 26343cc11f1773da49e23555c74a44ef5cbf3a4a Mon Sep 17 00:00:00 2001
From: easyonaadit <aaditya.alokdeshpande at amd.com>
Date: Fri, 20 Dec 2024 15:23:15 +0530
Subject: [PATCH] supporting dynamically sized allocas
---
.../Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 9 +-
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 50 +-
.../GlobalISel/dynamic-alloca-divergent.ll | 205 +++++-
.../test/CodeGen/AMDGPU/dynamic_stackalloc.ll | 613 +++++++++++++++++-
4 files changed, 804 insertions(+), 73 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
index d94c400ad14225..fb0e111d2c65a7 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -1191,8 +1191,13 @@ bool AMDGPURegisterBankInfo::applyMappingDynStackAlloc(
const RegisterBank *SizeBank = getRegBank(AllocSize, MRI, *TRI);
// TODO: Need to emit a wave reduction to get the maximum size.
- if (SizeBank != &AMDGPU::SGPRRegBank)
- return false;
+ if (SizeBank != &AMDGPU::SGPRRegBank){
+ auto WaveReduction = B.buildIntrinsic(Intrinsic::amdgcn_wave_reduce_umax,
+ {LLT::scalar(MRI.getType(AllocSize).getSizeInBits())})
+ .addUse(AllocSize)
+ .addImm(0);
+ AllocSize = WaveReduction.getReg(0);
+ }
LLT PtrTy = MRI.getType(Dst);
LLT IntPtrTy = LLT::scalar(PtrTy.getSizeInBits());
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 58b061f5c1af0d..fb316343c6c89f 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -4017,10 +4017,11 @@ SDValue SITargetLowering::LowerCall(CallLoweringInfo &CLI,
}
// This is similar to the default implementation in ExpandDYNAMIC_STACKALLOC,
-// except for stack growth direction(default: downwards, AMDGPU: upwards) and
-// applying the wave size scale to the increment amount.
-SDValue SITargetLowering::lowerDYNAMIC_STACKALLOCImpl(SDValue Op,
- SelectionDAG &DAG) const {
+// except for stack growth direction(default: downwards, AMDGPU: upwards),
+// applying the wave size scale to the increment amount,
+// and performing a wave-reduction for divergent allocation size.
+SDValue SITargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
+ SelectionDAG &DAG) const {
const MachineFunction &MF = DAG.getMachineFunction();
const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
@@ -4057,11 +4058,28 @@ SDValue SITargetLowering::lowerDYNAMIC_STACKALLOCImpl(SDValue Op,
DAG.getSignedConstant(-ScaledAlignment, dl, VT));
}
- SDValue ScaledSize = DAG.getNode(
- ISD::SHL, dl, VT, Size,
- DAG.getConstant(Subtarget->getWavefrontSizeLog2(), dl, MVT::i32));
-
- SDValue NewSP = DAG.getNode(ISD::ADD, dl, VT, BaseAddr, ScaledSize); // Value
+ SDValue NewSP;
+ if (isa<ConstantSDNode>(Op.getOperand(1))){
+ SDValue ScaledSize = DAG.getNode(
+ ISD::SHL, dl, VT, Size,
+ DAG.getConstant(Subtarget->getWavefrontSizeLog2(), dl, MVT::i32));
+ NewSP = DAG.getNode(ISD::ADD, dl, VT, BaseAddr, ScaledSize); // Value
+ }
+ else{
+ // performing a wave reduction to get the maximum size
+ SDValue WaveReduction =
+ DAG.getTargetConstant(Intrinsic::amdgcn_wave_reduce_umax, dl, MVT::i32);
+ Size = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32,
+ WaveReduction, Size, DAG.getConstant(0, dl, MVT::i32));
+ SDValue ScaledSize = DAG.getNode(
+ ISD::SHL, dl, VT, Size,
+ DAG.getConstant(Subtarget->getWavefrontSizeLog2(), dl, MVT::i32));
+ NewSP = DAG.getNode(ISD::ADD, dl, VT, BaseAddr, ScaledSize); // Value in vgpr.
+ SDValue ReadFirstLaneID =
+ DAG.getTargetConstant(Intrinsic::amdgcn_readfirstlane, dl, MVT::i32);
+ NewSP = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32,
+ ReadFirstLaneID, NewSP);
+ }
Chain = DAG.getCopyToReg(Chain, dl, SPReg, NewSP); // Output chain
Tmp2 = DAG.getCALLSEQ_END(Chain, 0, 0, SDValue(), dl);
@@ -4069,20 +4087,6 @@ SDValue SITargetLowering::lowerDYNAMIC_STACKALLOCImpl(SDValue Op,
return DAG.getMergeValues({BaseAddr, Tmp2}, dl);
}
-SDValue SITargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
- SelectionDAG &DAG) const {
- // We only handle constant sizes here to allow non-entry block, static sized
- // allocas. A truly dynamic value is more difficult to support because we
- // don't know if the size value is uniform or not. If the size isn't uniform,
- // we would need to do a wave reduction to get the maximum size to know how
- // much to increment the uniform stack pointer.
- SDValue Size = Op.getOperand(1);
- if (isa<ConstantSDNode>(Size))
- return lowerDYNAMIC_STACKALLOCImpl(Op, DAG); // Use "generic" expansion.
-
- return AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(Op, DAG);
-}
-
SDValue SITargetLowering::LowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const {
if (Op.getValueType() != MVT::i32)
return Op; // Defer to cannot select error.
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-divergent.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-divergent.ll
index aefcad491073fc..0fe1deeff11762 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-divergent.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-divergent.ll
@@ -1,10 +1,38 @@
-; RUN: not llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -global-isel-abort=2 -pass-remarks-missed="gisel.*" -verify-machineinstrs=0 -o /dev/null 2>&1 %s | FileCheck -check-prefix=ERR %s
-
-; ERR: remark: <unknown>:0:0: cannot select: %{{[0-9]+}}:sreg_32(p5) = G_DYN_STACKALLOC %{{[0-9]+}}:vgpr(s32), 1 (in function: kernel_dynamic_stackalloc_vgpr_align4)
-; ERR-NEXT: warning: Instruction selection used fallback path for kernel_dynamic_stackalloc_vgpr_align4
-; ERR-NEXT: error: <unknown>:0:0: in function kernel_dynamic_stackalloc_vgpr_align4 void (ptr addrspace(1)): unsupported dynamic alloca
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -global-isel-abort=2 -pass-remarks-missed="gisel.*" -verify-machineinstrs=0 < %s | FileCheck -check-prefix=DYN %s
define amdgpu_kernel void @kernel_dynamic_stackalloc_vgpr_align4(ptr addrspace(1) %ptr) {
+; DYN-LABEL: kernel_dynamic_stackalloc_vgpr_align4:
+; DYN: ; %bb.0:
+; DYN-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0
+; DYN-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; DYN-NEXT: s_add_u32 s0, s0, s17
+; DYN-NEXT: s_addc_u32 s1, s1, 0
+; DYN-NEXT: s_mov_b32 s6, 0
+; DYN-NEXT: s_waitcnt lgkmcnt(0)
+; DYN-NEXT: global_load_dword v0, v0, s[4:5]
+; DYN-NEXT: s_mov_b64 s[4:5], exec
+; DYN-NEXT: s_mov_b32 s33, 0
+; DYN-NEXT: s_movk_i32 s32, 0x400
+; DYN-NEXT: s_waitcnt vmcnt(0)
+; DYN-NEXT: v_lshl_add_u32 v0, v0, 2, 15
+; DYN-NEXT: v_and_b32_e32 v0, -16, v0
+; DYN-NEXT: .LBB0_1: ; =>This Inner Loop Header: Depth=1
+; DYN-NEXT: s_ff1_i32_b64 s7, s[4:5]
+; DYN-NEXT: v_readlane_b32 s8, v0, s7
+; DYN-NEXT: s_bitset0_b64 s[4:5], s7
+; DYN-NEXT: s_max_u32 s6, s6, s8
+; DYN-NEXT: s_cmp_lg_u64 s[4:5], 0
+; DYN-NEXT: s_cbranch_scc1 .LBB0_1
+; DYN-NEXT: ; %bb.2:
+; DYN-NEXT: s_mov_b32 s4, s32
+; DYN-NEXT: s_lshl_b32 s5, s6, 6
+; DYN-NEXT: v_mov_b32_e32 v0, 0x7b
+; DYN-NEXT: v_mov_b32_e32 v1, s4
+; DYN-NEXT: s_add_u32 s32, s4, s5
+; DYN-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen
+; DYN-NEXT: s_waitcnt vmcnt(0)
+; DYN-NEXT: s_endpgm
%id = call i32 @llvm.amdgcn.workitem.id.x()
%gep = getelementptr i32, ptr addrspace(1) %ptr, i32 %id
%n = load i32, ptr addrspace(1) %gep
@@ -13,11 +41,38 @@ define amdgpu_kernel void @kernel_dynamic_stackalloc_vgpr_align4(ptr addrspace(1
ret void
}
-; ERR: remark: <unknown>:0:0: cannot select: %{{[0-9]+}}:sreg_32(p5) = G_DYN_STACKALLOC %{{[0-9]+}}:vgpr(s32), 1 (in function: kernel_dynamic_stackalloc_vgpr_default_align)
-; ERR-NEXT: warning: Instruction selection used fallback path for kernel_dynamic_stackalloc_vgpr_default_align
-; ERR-NEXT: error: <unknown>:0:0: in function kernel_dynamic_stackalloc_vgpr_default_align void (ptr addrspace(1)): unsupported dynamic alloca
-
define amdgpu_kernel void @kernel_dynamic_stackalloc_vgpr_default_align(ptr addrspace(1) %ptr) {
+; DYN-LABEL: kernel_dynamic_stackalloc_vgpr_default_align:
+; DYN: ; %bb.0:
+; DYN-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0
+; DYN-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; DYN-NEXT: s_add_u32 s0, s0, s17
+; DYN-NEXT: s_addc_u32 s1, s1, 0
+; DYN-NEXT: s_mov_b32 s6, 0
+; DYN-NEXT: s_waitcnt lgkmcnt(0)
+; DYN-NEXT: global_load_dword v0, v0, s[4:5]
+; DYN-NEXT: s_mov_b64 s[4:5], exec
+; DYN-NEXT: s_mov_b32 s33, 0
+; DYN-NEXT: s_movk_i32 s32, 0x400
+; DYN-NEXT: s_waitcnt vmcnt(0)
+; DYN-NEXT: v_lshl_add_u32 v0, v0, 2, 15
+; DYN-NEXT: v_and_b32_e32 v0, -16, v0
+; DYN-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1
+; DYN-NEXT: s_ff1_i32_b64 s7, s[4:5]
+; DYN-NEXT: v_readlane_b32 s8, v0, s7
+; DYN-NEXT: s_bitset0_b64 s[4:5], s7
+; DYN-NEXT: s_max_u32 s6, s6, s8
+; DYN-NEXT: s_cmp_lg_u64 s[4:5], 0
+; DYN-NEXT: s_cbranch_scc1 .LBB1_1
+; DYN-NEXT: ; %bb.2:
+; DYN-NEXT: s_mov_b32 s4, s32
+; DYN-NEXT: s_lshl_b32 s5, s6, 6
+; DYN-NEXT: v_mov_b32_e32 v0, 0x7b
+; DYN-NEXT: v_mov_b32_e32 v1, s4
+; DYN-NEXT: s_add_u32 s32, s4, s5
+; DYN-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen
+; DYN-NEXT: s_waitcnt vmcnt(0)
+; DYN-NEXT: s_endpgm
%id = call i32 @llvm.amdgcn.workitem.id.x()
%gep = getelementptr i32, ptr addrspace(1) %ptr, i32 %id
%n = load i32, ptr addrspace(1) %gep
@@ -25,11 +80,40 @@ define amdgpu_kernel void @kernel_dynamic_stackalloc_vgpr_default_align(ptr addr
store volatile i32 123, ptr addrspace(5) %alloca
ret void
}
-; ERR: remark: <unknown>:0:0: cannot select: %{{[0-9]+}}:sreg_32(p5) = G_DYN_STACKALLOC %{{[0-9]+}}:vgpr(s32), 64 (in function: kernel_dynamic_stackalloc_vgpr_align64)
-; ERR-NEXT: warning: Instruction selection used fallback path for kernel_dynamic_stackalloc_vgpr_align64
-; ERR-NEXT: error: <unknown>:0:0: in function kernel_dynamic_stackalloc_vgpr_align64 void (ptr addrspace(1)): unsupported dynamic alloca
define amdgpu_kernel void @kernel_dynamic_stackalloc_vgpr_align64(ptr addrspace(1) %ptr) {
+; DYN-LABEL: kernel_dynamic_stackalloc_vgpr_align64:
+; DYN: ; %bb.0:
+; DYN-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0
+; DYN-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; DYN-NEXT: s_add_u32 s0, s0, s17
+; DYN-NEXT: s_addc_u32 s1, s1, 0
+; DYN-NEXT: s_mov_b32 s6, 0
+; DYN-NEXT: s_waitcnt lgkmcnt(0)
+; DYN-NEXT: global_load_dword v0, v0, s[4:5]
+; DYN-NEXT: s_mov_b64 s[4:5], exec
+; DYN-NEXT: s_mov_b32 s33, 0
+; DYN-NEXT: s_movk_i32 s32, 0x1000
+; DYN-NEXT: s_waitcnt vmcnt(0)
+; DYN-NEXT: v_lshl_add_u32 v0, v0, 2, 15
+; DYN-NEXT: v_and_b32_e32 v0, -16, v0
+; DYN-NEXT: .LBB2_1: ; =>This Inner Loop Header: Depth=1
+; DYN-NEXT: s_ff1_i32_b64 s7, s[4:5]
+; DYN-NEXT: v_readlane_b32 s8, v0, s7
+; DYN-NEXT: s_bitset0_b64 s[4:5], s7
+; DYN-NEXT: s_max_u32 s6, s6, s8
+; DYN-NEXT: s_cmp_lg_u64 s[4:5], 0
+; DYN-NEXT: s_cbranch_scc1 .LBB2_1
+; DYN-NEXT: ; %bb.2:
+; DYN-NEXT: s_add_u32 s5, s32, 0xfff
+; DYN-NEXT: s_and_b32 s5, s5, 0xfffff000
+; DYN-NEXT: s_lshl_b32 s4, s6, 6
+; DYN-NEXT: v_mov_b32_e32 v0, 0x7b
+; DYN-NEXT: v_mov_b32_e32 v1, s5
+; DYN-NEXT: s_add_u32 s32, s5, s4
+; DYN-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen
+; DYN-NEXT: s_waitcnt vmcnt(0)
+; DYN-NEXT: s_endpgm
%id = call i32 @llvm.amdgcn.workitem.id.x()
%gep = getelementptr i32, ptr addrspace(1) %ptr, i32 %id
%n = load i32, ptr addrspace(1) %gep
@@ -38,30 +122,105 @@ define amdgpu_kernel void @kernel_dynamic_stackalloc_vgpr_align64(ptr addrspace(
ret void
}
-; ERR: remark: <unknown>:0:0: cannot select: %{{[0-9]+}}:sreg_32(p5) = G_DYN_STACKALLOC %{{[0-9]+}}:vgpr(s32), 1 (in function: func_dynamic_stackalloc_vgpr_align4)
-; ERR-NEXT: warning: Instruction selection used fallback path for func_dynamic_stackalloc_vgpr_align4
-; ERR-NEXT: error: <unknown>:0:0: in function func_dynamic_stackalloc_vgpr_align4 void (i32): unsupported dynamic alloca
-
define void @func_dynamic_stackalloc_vgpr_align4(i32 %n) {
+; DYN-LABEL: func_dynamic_stackalloc_vgpr_align4:
+; DYN: ; %bb.0:
+; DYN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; DYN-NEXT: v_lshl_add_u32 v0, v0, 2, 15
+; DYN-NEXT: s_mov_b32 s9, s33
+; DYN-NEXT: v_and_b32_e32 v0, -16, v0
+; DYN-NEXT: s_mov_b64 s[4:5], exec
+; DYN-NEXT: s_mov_b32 s6, 0
+; DYN-NEXT: s_mov_b32 s33, s32
+; DYN-NEXT: s_addk_i32 s32, 0x400
+; DYN-NEXT: .LBB3_1: ; =>This Inner Loop Header: Depth=1
+; DYN-NEXT: s_ff1_i32_b64 s7, s[4:5]
+; DYN-NEXT: v_readlane_b32 s8, v0, s7
+; DYN-NEXT: s_bitset0_b64 s[4:5], s7
+; DYN-NEXT: s_max_u32 s6, s6, s8
+; DYN-NEXT: s_cmp_lg_u64 s[4:5], 0
+; DYN-NEXT: s_cbranch_scc1 .LBB3_1
+; DYN-NEXT: ; %bb.2:
+; DYN-NEXT: s_mov_b32 s4, s32
+; DYN-NEXT: s_lshl_b32 s5, s6, 6
+; DYN-NEXT: s_add_u32 s32, s4, s5
+; DYN-NEXT: v_mov_b32_e32 v0, 0x1c8
+; DYN-NEXT: v_mov_b32_e32 v1, s4
+; DYN-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen
+; DYN-NEXT: s_waitcnt vmcnt(0)
+; DYN-NEXT: s_addk_i32 s32, 0xfc00
+; DYN-NEXT: s_mov_b32 s33, s9
+; DYN-NEXT: s_setpc_b64 s[30:31]
%alloca = alloca i32, i32 %n, align 4, addrspace(5)
store volatile i32 456, ptr addrspace(5) %alloca
ret void
}
-; ERR: remark: <unknown>:0:0: cannot select: %{{[0-9]+}}:sreg_32(p5) = G_DYN_STACKALLOC %{{[0-9]+}}:vgpr(s32), 1 (in function: func_dynamic_stackalloc_vgpr_default_align)
-; ERR-NEXT: warning: Instruction selection used fallback path for func_dynamic_stackalloc_vgpr_default_align
-; ERR-NEXT: error: <unknown>:0:0: in function func_dynamic_stackalloc_vgpr_default_align void (i32): unsupported dynamic alloca
-
define void @func_dynamic_stackalloc_vgpr_default_align(i32 %n) {
+; DYN-LABEL: func_dynamic_stackalloc_vgpr_default_align:
+; DYN: ; %bb.0:
+; DYN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; DYN-NEXT: v_lshl_add_u32 v0, v0, 2, 15
+; DYN-NEXT: s_mov_b32 s9, s33
+; DYN-NEXT: v_and_b32_e32 v0, -16, v0
+; DYN-NEXT: s_mov_b64 s[4:5], exec
+; DYN-NEXT: s_mov_b32 s6, 0
+; DYN-NEXT: s_mov_b32 s33, s32
+; DYN-NEXT: s_addk_i32 s32, 0x400
+; DYN-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
+; DYN-NEXT: s_ff1_i32_b64 s7, s[4:5]
+; DYN-NEXT: v_readlane_b32 s8, v0, s7
+; DYN-NEXT: s_bitset0_b64 s[4:5], s7
+; DYN-NEXT: s_max_u32 s6, s6, s8
+; DYN-NEXT: s_cmp_lg_u64 s[4:5], 0
+; DYN-NEXT: s_cbranch_scc1 .LBB4_1
+; DYN-NEXT: ; %bb.2:
+; DYN-NEXT: s_mov_b32 s4, s32
+; DYN-NEXT: s_lshl_b32 s5, s6, 6
+; DYN-NEXT: s_add_u32 s32, s4, s5
+; DYN-NEXT: v_mov_b32_e32 v0, 0x1c8
+; DYN-NEXT: v_mov_b32_e32 v1, s4
+; DYN-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen
+; DYN-NEXT: s_waitcnt vmcnt(0)
+; DYN-NEXT: s_addk_i32 s32, 0xfc00
+; DYN-NEXT: s_mov_b32 s33, s9
+; DYN-NEXT: s_setpc_b64 s[30:31]
%alloca = alloca i32, i32 %n, addrspace(5)
store volatile i32 456, ptr addrspace(5) %alloca
ret void
}
-; ERR: remark: <unknown>:0:0: cannot select: %{{[0-9]+}}:sreg_32(p5) = G_DYN_STACKALLOC %{{[0-9]+}}:vgpr(s32), 64 (in function: func_dynamic_stackalloc_vgpr_align64)
-; ERR-NEXT: warning: Instruction selection used fallback path for func_dynamic_stackalloc_vgpr_align64
-; ERR-NEXT: error: <unknown>:0:0: in function func_dynamic_stackalloc_vgpr_align64 void (i32): unsupported dynamic alloca
define void @func_dynamic_stackalloc_vgpr_align64(i32 %n) {
+; DYN-LABEL: func_dynamic_stackalloc_vgpr_align64:
+; DYN: ; %bb.0:
+; DYN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; DYN-NEXT: v_lshl_add_u32 v0, v0, 2, 15
+; DYN-NEXT: s_mov_b32 s9, s33
+; DYN-NEXT: s_add_i32 s33, s32, 0xfc0
+; DYN-NEXT: v_and_b32_e32 v0, -16, v0
+; DYN-NEXT: s_mov_b64 s[4:5], exec
+; DYN-NEXT: s_mov_b32 s6, 0
+; DYN-NEXT: s_and_b32 s33, s33, 0xfffff000
+; DYN-NEXT: s_addk_i32 s32, 0x2000
+; DYN-NEXT: .LBB5_1: ; =>This Inner Loop Header: Depth=1
+; DYN-NEXT: s_ff1_i32_b64 s7, s[4:5]
+; DYN-NEXT: v_readlane_b32 s8, v0, s7
+; DYN-NEXT: s_bitset0_b64 s[4:5], s7
+; DYN-NEXT: s_max_u32 s6, s6, s8
+; DYN-NEXT: s_cmp_lg_u64 s[4:5], 0
+; DYN-NEXT: s_cbranch_scc1 .LBB5_1
+; DYN-NEXT: ; %bb.2:
+; DYN-NEXT: s_add_u32 s5, s32, 0xfff
+; DYN-NEXT: s_lshl_b32 s4, s6, 6
+; DYN-NEXT: s_and_b32 s5, s5, 0xfffff000
+; DYN-NEXT: s_add_u32 s32, s5, s4
+; DYN-NEXT: v_mov_b32_e32 v0, 0x1c8
+; DYN-NEXT: v_mov_b32_e32 v1, s5
+; DYN-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen
+; DYN-NEXT: s_waitcnt vmcnt(0)
+; DYN-NEXT: s_addk_i32 s32, 0xe000
+; DYN-NEXT: s_mov_b32 s33, s9
+; DYN-NEXT: s_setpc_b64 s[30:31]
%alloca = alloca i32, i32 %n, align 64, addrspace(5)
store volatile i32 456, ptr addrspace(5) %alloca
ret void
diff --git a/llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll b/llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll
index 73aa87e5c55d20..a75268844e7a52 100644
--- a/llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll
+++ b/llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll
@@ -1,64 +1,272 @@
-; RUN: not llc -mtriple=amdgcn-- -mcpu=tahiti -mattr=+promote-alloca -verify-machineinstrs < %s 2>&1 | FileCheck %s
-; RUN: not llc -mtriple=amdgcn-- -mcpu=tahiti -mattr=-promote-alloca -verify-machineinstrs < %s 2>&1 | FileCheck %s
-; RUN: not llc -mtriple=r600-- -mcpu=cypress < %s 2>&1 | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn-- -mcpu=gfx900 -mattr=+promote-alloca -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=DYN %s
+; RUN: llc -mtriple=amdgcn-- -mcpu=gfx900 -mattr=-promote-alloca -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=DYN %s
target datalayout = "A5"
-; CHECK: in function test_dynamic_stackalloc{{.*}}: unsupported dynamic alloca
define amdgpu_kernel void @test_dynamic_stackalloc_kernel_uniform(i32 %n) {
+; DYN-LABEL: test_dynamic_stackalloc_kernel_uniform:
+; DYN: ; %bb.0:
+; DYN-NEXT: s_mov_b32 s12, SCRATCH_RSRC_DWORD0
+; DYN-NEXT: s_load_dword s0, s[4:5], 0x24
+; DYN-NEXT: s_mov_b32 s13, SCRATCH_RSRC_DWORD1
+; DYN-NEXT: s_mov_b32 s14, -1
+; DYN-NEXT: s_mov_b32 s15, 0xe00000
+; DYN-NEXT: s_add_u32 s12, s12, s11
+; DYN-NEXT: s_addc_u32 s13, s13, 0
+; DYN-NEXT: s_waitcnt lgkmcnt(0)
+; DYN-NEXT: s_lshl_b32 s0, s0, 2
+; DYN-NEXT: s_add_i32 s0, s0, 15
+; DYN-NEXT: s_movk_i32 s32, 0x400
+; DYN-NEXT: s_and_b32 s0, s0, -16
+; DYN-NEXT: s_mov_b32 s1, s32
+; DYN-NEXT: v_mov_b32_e32 v0, 0x7b
+; DYN-NEXT: s_lshl_b32 s0, s0, 6
+; DYN-NEXT: s_mov_b32 s33, 0
+; DYN-NEXT: s_add_i32 s32, s1, s0
+; DYN-NEXT: buffer_store_dword v0, off, s[12:15], s1
+; DYN-NEXT: s_waitcnt vmcnt(0)
+; DYN-NEXT: s_endpgm
%alloca = alloca i32, i32 %n, addrspace(5)
store volatile i32 123, ptr addrspace(5) %alloca
ret void
}
-; CHECK: in function test_dynamic_stackalloc{{.*}}: unsupported dynamic alloca
define amdgpu_kernel void @test_dynamic_stackalloc_kernel_uniform_over_aligned(i32 %n) {
+; DYN-LABEL: test_dynamic_stackalloc_kernel_uniform_over_aligned:
+; DYN: ; %bb.0:
+; DYN-NEXT: s_mov_b32 s12, SCRATCH_RSRC_DWORD0
+; DYN-NEXT: s_load_dword s0, s[4:5], 0x24
+; DYN-NEXT: s_mov_b32 s13, SCRATCH_RSRC_DWORD1
+; DYN-NEXT: s_mov_b32 s14, -1
+; DYN-NEXT: s_mov_b32 s15, 0xe00000
+; DYN-NEXT: s_add_u32 s12, s12, s11
+; DYN-NEXT: s_movk_i32 s32, 0x2000
+; DYN-NEXT: s_addc_u32 s13, s13, 0
+; DYN-NEXT: s_waitcnt lgkmcnt(0)
+; DYN-NEXT: s_lshl_b32 s0, s0, 2
+; DYN-NEXT: s_add_i32 s1, s32, 0x1fff
+; DYN-NEXT: s_add_i32 s0, s0, 15
+; DYN-NEXT: s_and_b32 s1, s1, 0xffffe000
+; DYN-NEXT: s_and_b32 s0, s0, -16
+; DYN-NEXT: v_mov_b32_e32 v0, 10
+; DYN-NEXT: s_lshl_b32 s0, s0, 6
+; DYN-NEXT: v_mov_b32_e32 v1, s1
+; DYN-NEXT: s_mov_b32 s33, 0
+; DYN-NEXT: s_add_i32 s32, s1, s0
+; DYN-NEXT: buffer_store_dword v0, v1, s[12:15], 0 offen
+; DYN-NEXT: s_waitcnt vmcnt(0)
+; DYN-NEXT: s_endpgm
%alloca = alloca i32, i32 %n, align 128, addrspace(5)
store volatile i32 10, ptr addrspace(5) %alloca
ret void
}
-; CHECK: in function test_dynamic_stackalloc{{.*}}: unsupported dynamic alloca
define amdgpu_kernel void @test_dynamic_stackalloc_kernel_uniform_under_aligned(i32 %n) {
+; DYN-LABEL: test_dynamic_stackalloc_kernel_uniform_under_aligned:
+; DYN: ; %bb.0:
+; DYN-NEXT: s_mov_b32 s12, SCRATCH_RSRC_DWORD0
+; DYN-NEXT: s_load_dword s0, s[4:5], 0x24
+; DYN-NEXT: s_mov_b32 s13, SCRATCH_RSRC_DWORD1
+; DYN-NEXT: s_mov_b32 s14, -1
+; DYN-NEXT: s_mov_b32 s15, 0xe00000
+; DYN-NEXT: s_add_u32 s12, s12, s11
+; DYN-NEXT: s_addc_u32 s13, s13, 0
+; DYN-NEXT: s_waitcnt lgkmcnt(0)
+; DYN-NEXT: s_lshl_b32 s0, s0, 2
+; DYN-NEXT: s_add_i32 s0, s0, 15
+; DYN-NEXT: s_movk_i32 s32, 0x400
+; DYN-NEXT: s_and_b32 s0, s0, -16
+; DYN-NEXT: s_mov_b32 s1, s32
+; DYN-NEXT: v_mov_b32_e32 v0, 22
+; DYN-NEXT: s_lshl_b32 s0, s0, 6
+; DYN-NEXT: s_mov_b32 s33, 0
+; DYN-NEXT: s_add_i32 s32, s1, s0
+; DYN-NEXT: buffer_store_dword v0, off, s[12:15], s1
+; DYN-NEXT: s_waitcnt vmcnt(0)
+; DYN-NEXT: s_endpgm
%alloca = alloca i32, i32 %n, align 2, addrspace(5)
store volatile i32 22, ptr addrspace(5) %alloca
ret void
}
-; CHECK: in function test_dynamic_stackalloc{{.*}}: unsupported dynamic alloca
define amdgpu_kernel void @test_dynamic_stackalloc_kernel_divergent() {
+; DYN-LABEL: test_dynamic_stackalloc_kernel_divergent:
+; DYN: ; %bb.0:
+; DYN-NEXT: s_mov_b32 s12, SCRATCH_RSRC_DWORD0
+; DYN-NEXT: s_mov_b32 s13, SCRATCH_RSRC_DWORD1
+; DYN-NEXT: s_mov_b32 s14, -1
+; DYN-NEXT: s_mov_b32 s15, 0xe00000
+; DYN-NEXT: s_add_u32 s12, s12, s11
+; DYN-NEXT: v_lshl_add_u32 v0, v0, 2, 15
+; DYN-NEXT: s_addc_u32 s13, s13, 0
+; DYN-NEXT: v_and_b32_e32 v0, 0x1ff0, v0
+; DYN-NEXT: s_mov_b64 s[0:1], exec
+; DYN-NEXT: s_mov_b32 s2, 0
+; DYN-NEXT: s_mov_b32 s33, 0
+; DYN-NEXT: s_movk_i32 s32, 0x400
+; DYN-NEXT: .LBB3_1: ; =>This Inner Loop Header: Depth=1
+; DYN-NEXT: s_ff1_i32_b64 s3, s[0:1]
+; DYN-NEXT: v_readlane_b32 s4, v0, s3
+; DYN-NEXT: s_bitset0_b64 s[0:1], s3
+; DYN-NEXT: s_max_u32 s2, s2, s4
+; DYN-NEXT: s_cmp_lg_u64 s[0:1], 0
+; DYN-NEXT: s_cbranch_scc1 .LBB3_1
+; DYN-NEXT: ; %bb.2:
+; DYN-NEXT: s_mov_b32 s0, s32
+; DYN-NEXT: v_mov_b32_e32 v0, s0
+; DYN-NEXT: v_lshl_add_u32 v0, s2, 6, v0
+; DYN-NEXT: v_readfirstlane_b32 s32, v0
+; DYN-NEXT: v_mov_b32_e32 v0, 0x7b
+; DYN-NEXT: buffer_store_dword v0, off, s[12:15], s0
+; DYN-NEXT: s_waitcnt vmcnt(0)
+; DYN-NEXT: s_endpgm
%idx = call i32 @llvm.amdgcn.workitem.id.x()
%alloca = alloca float, i32 %idx, addrspace(5)
store volatile i32 123, ptr addrspace(5) %alloca
ret void
}
-; CHECK: in function test_dynamic_stackalloc{{.*}}: unsupported dynamic alloca
define amdgpu_kernel void @test_dynamic_stackalloc_kernel_divergent_over_aligned() {
+; DYN-LABEL: test_dynamic_stackalloc_kernel_divergent_over_aligned:
+; DYN: ; %bb.0:
+; DYN-NEXT: s_mov_b32 s12, SCRATCH_RSRC_DWORD0
+; DYN-NEXT: s_mov_b32 s13, SCRATCH_RSRC_DWORD1
+; DYN-NEXT: s_mov_b32 s14, -1
+; DYN-NEXT: s_mov_b32 s15, 0xe00000
+; DYN-NEXT: s_add_u32 s12, s12, s11
+; DYN-NEXT: v_lshl_add_u32 v0, v0, 2, 15
+; DYN-NEXT: s_addc_u32 s13, s13, 0
+; DYN-NEXT: v_and_b32_e32 v0, 0x1ff0, v0
+; DYN-NEXT: s_mov_b64 s[0:1], exec
+; DYN-NEXT: s_mov_b32 s2, 0
+; DYN-NEXT: s_mov_b32 s33, 0
+; DYN-NEXT: s_movk_i32 s32, 0x2000
+; DYN-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
+; DYN-NEXT: s_ff1_i32_b64 s3, s[0:1]
+; DYN-NEXT: v_readlane_b32 s4, v0, s3
+; DYN-NEXT: s_bitset0_b64 s[0:1], s3
+; DYN-NEXT: s_max_u32 s2, s2, s4
+; DYN-NEXT: s_cmp_lg_u64 s[0:1], 0
+; DYN-NEXT: s_cbranch_scc1 .LBB4_1
+; DYN-NEXT: ; %bb.2:
+; DYN-NEXT: s_add_i32 s0, s32, 0x1fff
+; DYN-NEXT: s_and_b32 s0, s0, 0xffffe000
+; DYN-NEXT: v_mov_b32_e32 v0, s0
+; DYN-NEXT: v_lshl_add_u32 v1, s2, 6, v0
+; DYN-NEXT: v_readfirstlane_b32 s32, v1
+; DYN-NEXT: v_mov_b32_e32 v1, 0x1bc
+; DYN-NEXT: buffer_store_dword v1, v0, s[12:15], 0 offen
+; DYN-NEXT: s_waitcnt vmcnt(0)
+; DYN-NEXT: s_endpgm
%idx = call i32 @llvm.amdgcn.workitem.id.x()
%alloca = alloca i32, i32 %idx, align 128, addrspace(5)
store volatile i32 444, ptr addrspace(5) %alloca
ret void
}
-; CHECK: in function test_dynamic_stackalloc{{.*}}: unsupported dynamic alloca
define amdgpu_kernel void @test_dynamic_stackalloc_kernel_divergent_under_aligned() {
+; DYN-LABEL: test_dynamic_stackalloc_kernel_divergent_under_aligned:
+; DYN: ; %bb.0:
+; DYN-NEXT: s_mov_b32 s12, SCRATCH_RSRC_DWORD0
+; DYN-NEXT: s_mov_b32 s13, SCRATCH_RSRC_DWORD1
+; DYN-NEXT: s_mov_b32 s14, -1
+; DYN-NEXT: s_mov_b32 s15, 0xe00000
+; DYN-NEXT: s_add_u32 s12, s12, s11
+; DYN-NEXT: s_addc_u32 s13, s13, 0
+; DYN-NEXT: v_lshlrev_b32_e32 v0, 4, v0
+; DYN-NEXT: s_mov_b64 s[0:1], exec
+; DYN-NEXT: s_mov_b32 s2, 0
+; DYN-NEXT: s_mov_b32 s33, 0
+; DYN-NEXT: s_movk_i32 s32, 0x400
+; DYN-NEXT: .LBB5_1: ; =>This Inner Loop Header: Depth=1
+; DYN-NEXT: s_ff1_i32_b64 s3, s[0:1]
+; DYN-NEXT: v_readlane_b32 s4, v0, s3
+; DYN-NEXT: s_bitset0_b64 s[0:1], s3
+; DYN-NEXT: s_max_u32 s2, s2, s4
+; DYN-NEXT: s_cmp_lg_u64 s[0:1], 0
+; DYN-NEXT: s_cbranch_scc1 .LBB5_1
+; DYN-NEXT: ; %bb.2:
+; DYN-NEXT: s_mov_b32 s0, s32
+; DYN-NEXT: v_mov_b32_e32 v0, s0
+; DYN-NEXT: v_lshl_add_u32 v0, s2, 6, v0
+; DYN-NEXT: v_readfirstlane_b32 s32, v0
+; DYN-NEXT: v_mov_b32_e32 v0, 0x29a
+; DYN-NEXT: buffer_store_dword v0, off, s[12:15], s0
+; DYN-NEXT: s_waitcnt vmcnt(0)
+; DYN-NEXT: s_endpgm
%idx = call i32 @llvm.amdgcn.workitem.id.x()
%alloca = alloca i128, i32 %idx, align 2, addrspace(5)
store volatile i32 666, ptr addrspace(5) %alloca
ret void
}
-; CHECK: in function test_dynamic_stackalloc{{.*}}: unsupported dynamic alloca
-; CHECK: in function test_dynamic_stackalloc{{.*}}: unsupported dynamic alloca
-; CHECK: in function test_dynamic_stackalloc{{.*}}: unsupported dynamic alloca
define amdgpu_kernel void @test_dynamic_stackalloc_kernel_multiple_allocas(i32 %n, i32 %m) {
+; DYN-LABEL: test_dynamic_stackalloc_kernel_multiple_allocas:
+; DYN: ; %bb.0: ; %entry
+; DYN-NEXT: s_mov_b32 s12, SCRATCH_RSRC_DWORD0
+; DYN-NEXT: s_mov_b32 s13, SCRATCH_RSRC_DWORD1
+; DYN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; DYN-NEXT: s_mov_b32 s14, -1
+; DYN-NEXT: s_mov_b32 s15, 0xe00000
+; DYN-NEXT: s_add_u32 s12, s12, s11
+; DYN-NEXT: s_addc_u32 s13, s13, 0
+; DYN-NEXT: s_waitcnt lgkmcnt(0)
+; DYN-NEXT: s_cmp_lg_u32 s0, 0
+; DYN-NEXT: s_mov_b32 s4, 0
+; DYN-NEXT: s_mov_b32 s33, 0
+; DYN-NEXT: s_movk_i32 s32, 0x2000
+; DYN-NEXT: s_cbranch_scc1 .LBB6_4
+; DYN-NEXT: ; %bb.1: ; %bb.0
+; DYN-NEXT: s_lshl_b32 s1, s1, 2
+; DYN-NEXT: s_add_i32 s1, s1, 15
+; DYN-NEXT: s_add_i32 s2, s32, 0xfff
+; DYN-NEXT: s_and_b32 s1, s1, -16
+; DYN-NEXT: v_lshl_add_u32 v0, v0, 2, 15
+; DYN-NEXT: s_and_b32 s5, s2, 0xfffff000
+; DYN-NEXT: s_lshl_b32 s1, s1, 6
+; DYN-NEXT: v_and_b32_e32 v0, 0x1ff0, v0
+; DYN-NEXT: s_mov_b64 s[2:3], exec
+; DYN-NEXT: s_add_i32 s32, s5, s1
+; DYN-NEXT: .LBB6_2: ; =>This Inner Loop Header: Depth=1
+; DYN-NEXT: s_ff1_i32_b64 s1, s[2:3]
+; DYN-NEXT: v_readlane_b32 s6, v0, s1
+; DYN-NEXT: s_bitset0_b64 s[2:3], s1
+; DYN-NEXT: s_max_u32 s4, s4, s6
+; DYN-NEXT: s_cmp_lg_u64 s[2:3], 0
+; DYN-NEXT: s_cbranch_scc1 .LBB6_2
+; DYN-NEXT: ; %bb.3:
+; DYN-NEXT: s_mov_b32 s1, s32
+; DYN-NEXT: v_mov_b32_e32 v0, s1
+; DYN-NEXT: v_lshl_add_u32 v0, s4, 6, v0
+; DYN-NEXT: v_readfirstlane_b32 s32, v0
+; DYN-NEXT: v_mov_b32_e32 v0, 3
+; DYN-NEXT: v_mov_b32_e32 v1, s5
+; DYN-NEXT: buffer_store_dword v0, v1, s[12:15], 0 offen
+; DYN-NEXT: s_waitcnt vmcnt(0)
+; DYN-NEXT: v_mov_b32_e32 v0, 4
+; DYN-NEXT: buffer_store_dword v0, off, s[12:15], s1
+; DYN-NEXT: s_waitcnt vmcnt(0)
+; DYN-NEXT: .LBB6_4: ; %bb.1
+; DYN-NEXT: s_lshl_b32 s0, s0, 2
+; DYN-NEXT: s_add_i32 s0, s0, 15
+; DYN-NEXT: s_and_b32 s0, s0, -16
+; DYN-NEXT: v_mov_b32_e32 v0, 1
+; DYN-NEXT: s_lshl_b32 s0, s0, 6
+; DYN-NEXT: s_mov_b32 s1, s32
+; DYN-NEXT: buffer_store_dword v0, off, s[12:15], s33
+; DYN-NEXT: s_waitcnt vmcnt(0)
+; DYN-NEXT: v_mov_b32_e32 v0, 2
+; DYN-NEXT: s_add_i32 s32, s1, s0
+; DYN-NEXT: buffer_store_dword v0, off, s[12:15], s1
+; DYN-NEXT: s_waitcnt vmcnt(0)
+; DYN-NEXT: s_endpgm
entry:
%cond = icmp eq i32 %n, 0
%alloca1 = alloca i32, i32 8, addrspace(5)
@@ -77,10 +285,59 @@ bb.1:
ret void
}
-; CHECK: in function test_dynamic_stackalloc{{.*}}: unsupported dynamic alloca
-; CHECK: in function test_dynamic_stackalloc{{.*}}: unsupported dynamic alloca
define amdgpu_kernel void @test_dynamic_stackalloc_kernel_control_flow(i32 %n, i32 %m) {
+; DYN-LABEL: test_dynamic_stackalloc_kernel_control_flow:
+; DYN: ; %bb.0: ; %entry
+; DYN-NEXT: s_mov_b32 s12, SCRATCH_RSRC_DWORD0
+; DYN-NEXT: s_mov_b32 s13, SCRATCH_RSRC_DWORD1
+; DYN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; DYN-NEXT: s_mov_b32 s14, -1
+; DYN-NEXT: s_mov_b32 s15, 0xe00000
+; DYN-NEXT: s_add_u32 s12, s12, s11
+; DYN-NEXT: s_addc_u32 s13, s13, 0
+; DYN-NEXT: s_waitcnt lgkmcnt(0)
+; DYN-NEXT: s_cmp_lg_u32 s0, 0
+; DYN-NEXT: s_mov_b32 s0, 0
+; DYN-NEXT: s_mov_b32 s33, 0
+; DYN-NEXT: s_movk_i32 s32, 0x1000
+; DYN-NEXT: s_cbranch_scc0 .LBB7_6
+; DYN-NEXT: ; %bb.1: ; %bb.1
+; DYN-NEXT: v_lshl_add_u32 v0, v0, 2, 15
+; DYN-NEXT: v_and_b32_e32 v0, 0x1ff0, v0
+; DYN-NEXT: s_mov_b64 s[2:3], exec
+; DYN-NEXT: .LBB7_2: ; =>This Inner Loop Header: Depth=1
+; DYN-NEXT: s_ff1_i32_b64 s4, s[2:3]
+; DYN-NEXT: v_readlane_b32 s5, v0, s4
+; DYN-NEXT: s_bitset0_b64 s[2:3], s4
+; DYN-NEXT: s_max_u32 s0, s0, s5
+; DYN-NEXT: s_cmp_lg_u64 s[2:3], 0
+; DYN-NEXT: s_cbranch_scc1 .LBB7_2
+; DYN-NEXT: ; %bb.3:
+; DYN-NEXT: s_mov_b32 s2, s32
+; DYN-NEXT: v_mov_b32_e32 v0, s2
+; DYN-NEXT: v_lshl_add_u32 v0, s0, 6, v0
+; DYN-NEXT: v_readfirstlane_b32 s32, v0
+; DYN-NEXT: v_mov_b32_e32 v0, 1
+; DYN-NEXT: buffer_store_dword v0, off, s[12:15], s2
+; DYN-NEXT: s_waitcnt vmcnt(0)
+; DYN-NEXT: s_cbranch_execnz .LBB7_5
+; DYN-NEXT: .LBB7_4: ; %bb.0
+; DYN-NEXT: s_lshl_b32 s1, s1, 2
+; DYN-NEXT: s_add_i32 s0, s32, 0xfff
+; DYN-NEXT: s_add_i32 s1, s1, 15
+; DYN-NEXT: s_and_b32 s0, s0, 0xfffff000
+; DYN-NEXT: s_and_b32 s1, s1, -16
+; DYN-NEXT: s_lshl_b32 s1, s1, 6
+; DYN-NEXT: v_mov_b32_e32 v0, 2
+; DYN-NEXT: v_mov_b32_e32 v1, s0
+; DYN-NEXT: s_add_i32 s32, s0, s1
+; DYN-NEXT: buffer_store_dword v0, v1, s[12:15], 0 offen
+; DYN-NEXT: s_waitcnt vmcnt(0)
+; DYN-NEXT: .LBB7_5: ; %bb.2
+; DYN-NEXT: s_endpgm
+; DYN-NEXT: .LBB7_6:
+; DYN-NEXT: s_branch .LBB7_4
entry:
%cond = icmp eq i32 %n, 0
br i1 %cond, label %bb.0, label %bb.1
@@ -97,62 +354,307 @@ bb.2:
ret void
}
-; CHECK: in function test_dynamic_stackalloc{{.*}}: unsupported dynamic alloca
define void @test_dynamic_stackalloc_device_uniform(i32 %n) {
+; DYN-LABEL: test_dynamic_stackalloc_device_uniform:
+; DYN: ; %bb.0:
+; DYN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; DYN-NEXT: v_lshl_add_u32 v0, v0, 2, 15
+; DYN-NEXT: s_mov_b32 s9, s33
+; DYN-NEXT: v_and_b32_e32 v0, -16, v0
+; DYN-NEXT: s_mov_b64 s[4:5], exec
+; DYN-NEXT: s_mov_b32 s6, 0
+; DYN-NEXT: s_mov_b32 s33, s32
+; DYN-NEXT: s_addk_i32 s32, 0x400
+; DYN-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
+; DYN-NEXT: s_ff1_i32_b64 s7, s[4:5]
+; DYN-NEXT: v_readlane_b32 s8, v0, s7
+; DYN-NEXT: s_bitset0_b64 s[4:5], s7
+; DYN-NEXT: s_max_u32 s6, s6, s8
+; DYN-NEXT: s_cmp_lg_u64 s[4:5], 0
+; DYN-NEXT: s_cbranch_scc1 .LBB8_1
+; DYN-NEXT: ; %bb.2:
+; DYN-NEXT: s_mov_b32 s4, s32
+; DYN-NEXT: v_mov_b32_e32 v0, s4
+; DYN-NEXT: v_lshl_add_u32 v0, s6, 6, v0
+; DYN-NEXT: v_readfirstlane_b32 s32, v0
+; DYN-NEXT: v_mov_b32_e32 v0, 0x7b
+; DYN-NEXT: buffer_store_dword v0, off, s[0:3], s4
+; DYN-NEXT: s_waitcnt vmcnt(0)
+; DYN-NEXT: s_addk_i32 s32, 0xfc00
+; DYN-NEXT: s_mov_b32 s33, s9
+; DYN-NEXT: s_setpc_b64 s[30:31]
%alloca = alloca i32, i32 %n, addrspace(5)
store volatile i32 123, ptr addrspace(5) %alloca
ret void
}
-; CHECK: in function test_dynamic_stackalloc{{.*}}: unsupported dynamic alloca
define void @test_dynamic_stackalloc_device_uniform_over_aligned(i32 %n) {
+; DYN-LABEL: test_dynamic_stackalloc_device_uniform_over_aligned:
+; DYN: ; %bb.0:
+; DYN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; DYN-NEXT: v_lshl_add_u32 v0, v0, 2, 15
+; DYN-NEXT: s_mov_b32 s9, s33
+; DYN-NEXT: s_add_i32 s33, s32, 0x1fc0
+; DYN-NEXT: v_and_b32_e32 v0, -16, v0
+; DYN-NEXT: s_mov_b64 s[4:5], exec
+; DYN-NEXT: s_mov_b32 s6, 0
+; DYN-NEXT: s_and_b32 s33, s33, 0xffffe000
+; DYN-NEXT: s_addk_i32 s32, 0x4000
+; DYN-NEXT: .LBB9_1: ; =>This Inner Loop Header: Depth=1
+; DYN-NEXT: s_ff1_i32_b64 s7, s[4:5]
+; DYN-NEXT: v_readlane_b32 s8, v0, s7
+; DYN-NEXT: s_bitset0_b64 s[4:5], s7
+; DYN-NEXT: s_max_u32 s6, s6, s8
+; DYN-NEXT: s_cmp_lg_u64 s[4:5], 0
+; DYN-NEXT: s_cbranch_scc1 .LBB9_1
+; DYN-NEXT: ; %bb.2:
+; DYN-NEXT: s_add_i32 s4, s32, 0x1fff
+; DYN-NEXT: s_and_b32 s4, s4, 0xffffe000
+; DYN-NEXT: v_mov_b32_e32 v0, s4
+; DYN-NEXT: v_lshl_add_u32 v1, s6, 6, v0
+; DYN-NEXT: v_readfirstlane_b32 s32, v1
+; DYN-NEXT: v_mov_b32_e32 v1, 10
+; DYN-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
+; DYN-NEXT: s_waitcnt vmcnt(0)
+; DYN-NEXT: s_addk_i32 s32, 0xc000
+; DYN-NEXT: s_mov_b32 s33, s9
+; DYN-NEXT: s_setpc_b64 s[30:31]
%alloca = alloca i32, i32 %n, align 128, addrspace(5)
store volatile i32 10, ptr addrspace(5) %alloca
ret void
}
-; CHECK: in function test_dynamic_stackalloc{{.*}}: unsupported dynamic alloca
define void @test_dynamic_stackalloc_device_uniform_under_aligned(i32 %n) {
+; DYN-LABEL: test_dynamic_stackalloc_device_uniform_under_aligned:
+; DYN: ; %bb.0:
+; DYN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; DYN-NEXT: v_lshl_add_u32 v0, v0, 2, 15
+; DYN-NEXT: s_mov_b32 s9, s33
+; DYN-NEXT: v_and_b32_e32 v0, -16, v0
+; DYN-NEXT: s_mov_b64 s[4:5], exec
+; DYN-NEXT: s_mov_b32 s6, 0
+; DYN-NEXT: s_mov_b32 s33, s32
+; DYN-NEXT: s_addk_i32 s32, 0x400
+; DYN-NEXT: .LBB10_1: ; =>This Inner Loop Header: Depth=1
+; DYN-NEXT: s_ff1_i32_b64 s7, s[4:5]
+; DYN-NEXT: v_readlane_b32 s8, v0, s7
+; DYN-NEXT: s_bitset0_b64 s[4:5], s7
+; DYN-NEXT: s_max_u32 s6, s6, s8
+; DYN-NEXT: s_cmp_lg_u64 s[4:5], 0
+; DYN-NEXT: s_cbranch_scc1 .LBB10_1
+; DYN-NEXT: ; %bb.2:
+; DYN-NEXT: s_mov_b32 s4, s32
+; DYN-NEXT: v_mov_b32_e32 v0, s4
+; DYN-NEXT: v_lshl_add_u32 v0, s6, 6, v0
+; DYN-NEXT: v_readfirstlane_b32 s32, v0
+; DYN-NEXT: v_mov_b32_e32 v0, 22
+; DYN-NEXT: buffer_store_dword v0, off, s[0:3], s4
+; DYN-NEXT: s_waitcnt vmcnt(0)
+; DYN-NEXT: s_addk_i32 s32, 0xfc00
+; DYN-NEXT: s_mov_b32 s33, s9
+; DYN-NEXT: s_setpc_b64 s[30:31]
%alloca = alloca i32, i32 %n, align 2, addrspace(5)
store volatile i32 22, ptr addrspace(5) %alloca
ret void
}
-; CHECK: in function test_dynamic_stackalloc{{.*}}: unsupported dynamic alloca
define void @test_dynamic_stackalloc_device_divergent() {
+; DYN-LABEL: test_dynamic_stackalloc_device_divergent:
+; DYN: ; %bb.0:
+; DYN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; DYN-NEXT: v_and_b32_e32 v0, 0x3ff, v31
+; DYN-NEXT: v_lshl_add_u32 v0, v0, 2, 15
+; DYN-NEXT: s_mov_b32 s9, s33
+; DYN-NEXT: v_and_b32_e32 v0, 0x1ff0, v0
+; DYN-NEXT: s_mov_b64 s[4:5], exec
+; DYN-NEXT: s_mov_b32 s6, 0
+; DYN-NEXT: s_mov_b32 s33, s32
+; DYN-NEXT: s_addk_i32 s32, 0x400
+; DYN-NEXT: .LBB11_1: ; =>This Inner Loop Header: Depth=1
+; DYN-NEXT: s_ff1_i32_b64 s7, s[4:5]
+; DYN-NEXT: v_readlane_b32 s8, v0, s7
+; DYN-NEXT: s_bitset0_b64 s[4:5], s7
+; DYN-NEXT: s_max_u32 s6, s6, s8
+; DYN-NEXT: s_cmp_lg_u64 s[4:5], 0
+; DYN-NEXT: s_cbranch_scc1 .LBB11_1
+; DYN-NEXT: ; %bb.2:
+; DYN-NEXT: s_mov_b32 s4, s32
+; DYN-NEXT: v_mov_b32_e32 v0, s4
+; DYN-NEXT: v_lshl_add_u32 v0, s6, 6, v0
+; DYN-NEXT: v_readfirstlane_b32 s32, v0
+; DYN-NEXT: v_mov_b32_e32 v0, 0x7b
+; DYN-NEXT: buffer_store_dword v0, off, s[0:3], s4
+; DYN-NEXT: s_waitcnt vmcnt(0)
+; DYN-NEXT: s_addk_i32 s32, 0xfc00
+; DYN-NEXT: s_mov_b32 s33, s9
+; DYN-NEXT: s_setpc_b64 s[30:31]
%idx = call i32 @llvm.amdgcn.workitem.id.x()
%alloca = alloca i32, i32 %idx, addrspace(5)
store volatile i32 123, ptr addrspace(5) %alloca
ret void
}
-; CHECK: in function test_dynamic_stackalloc{{.*}}: unsupported dynamic alloca
define void @test_dynamic_stackalloc_device_divergent_over_aligned() {
+; DYN-LABEL: test_dynamic_stackalloc_device_divergent_over_aligned:
+; DYN: ; %bb.0:
+; DYN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; DYN-NEXT: s_mov_b32 s10, s33
+; DYN-NEXT: s_add_i32 s33, s32, 0x1fc0
+; DYN-NEXT: s_addk_i32 s32, 0x4000
+; DYN-NEXT: v_and_b32_e32 v0, 0x3ff, v31
+; DYN-NEXT: s_add_i32 s4, s32, 0x1fff
+; DYN-NEXT: v_lshl_add_u32 v0, v0, 2, 15
+; DYN-NEXT: s_and_b32 s6, s4, 0xffffe000
+; DYN-NEXT: v_and_b32_e32 v0, 0x1ff0, v0
+; DYN-NEXT: s_mov_b64 s[4:5], exec
+; DYN-NEXT: s_mov_b32 s7, 0
+; DYN-NEXT: s_and_b32 s33, s33, 0xffffe000
+; DYN-NEXT: .LBB12_1: ; =>This Inner Loop Header: Depth=1
+; DYN-NEXT: s_ff1_i32_b64 s8, s[4:5]
+; DYN-NEXT: v_readlane_b32 s9, v0, s8
+; DYN-NEXT: s_bitset0_b64 s[4:5], s8
+; DYN-NEXT: s_max_u32 s7, s7, s9
+; DYN-NEXT: s_cmp_lg_u64 s[4:5], 0
+; DYN-NEXT: s_cbranch_scc1 .LBB12_1
+; DYN-NEXT: ; %bb.2:
+; DYN-NEXT: v_mov_b32_e32 v0, s6
+; DYN-NEXT: v_lshl_add_u32 v1, s7, 6, v0
+; DYN-NEXT: v_readfirstlane_b32 s32, v1
+; DYN-NEXT: v_mov_b32_e32 v1, 0x1bc
+; DYN-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
+; DYN-NEXT: s_waitcnt vmcnt(0)
+; DYN-NEXT: s_addk_i32 s32, 0xc000
+; DYN-NEXT: s_mov_b32 s33, s10
+; DYN-NEXT: s_setpc_b64 s[30:31]
%idx = call i32 @llvm.amdgcn.workitem.id.x()
%alloca = alloca i32, i32 %idx, align 128, addrspace(5)
store volatile i32 444, ptr addrspace(5) %alloca
ret void
}
-; CHECK: in function test_dynamic_stackalloc{{.*}}: unsupported dynamic alloca
define void @test_dynamic_stackalloc_device_divergent_under_aligned() {
+; DYN-LABEL: test_dynamic_stackalloc_device_divergent_under_aligned:
+; DYN: ; %bb.0:
+; DYN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; DYN-NEXT: v_and_b32_e32 v0, 0x3ff, v31
+; DYN-NEXT: v_lshl_add_u32 v0, v0, 2, 15
+; DYN-NEXT: s_mov_b32 s9, s33
+; DYN-NEXT: v_and_b32_e32 v0, 0x1ff0, v0
+; DYN-NEXT: s_mov_b64 s[4:5], exec
+; DYN-NEXT: s_mov_b32 s6, 0
+; DYN-NEXT: s_mov_b32 s33, s32
+; DYN-NEXT: s_addk_i32 s32, 0x400
+; DYN-NEXT: .LBB13_1: ; =>This Inner Loop Header: Depth=1
+; DYN-NEXT: s_ff1_i32_b64 s7, s[4:5]
+; DYN-NEXT: v_readlane_b32 s8, v0, s7
+; DYN-NEXT: s_bitset0_b64 s[4:5], s7
+; DYN-NEXT: s_max_u32 s6, s6, s8
+; DYN-NEXT: s_cmp_lg_u64 s[4:5], 0
+; DYN-NEXT: s_cbranch_scc1 .LBB13_1
+; DYN-NEXT: ; %bb.2:
+; DYN-NEXT: s_mov_b32 s4, s32
+; DYN-NEXT: v_mov_b32_e32 v0, s4
+; DYN-NEXT: v_lshl_add_u32 v0, s6, 6, v0
+; DYN-NEXT: v_readfirstlane_b32 s32, v0
+; DYN-NEXT: v_mov_b32_e32 v0, 0x29a
+; DYN-NEXT: buffer_store_dword v0, off, s[0:3], s4
+; DYN-NEXT: s_waitcnt vmcnt(0)
+; DYN-NEXT: s_addk_i32 s32, 0xfc00
+; DYN-NEXT: s_mov_b32 s33, s9
+; DYN-NEXT: s_setpc_b64 s[30:31]
%idx = call i32 @llvm.amdgcn.workitem.id.x()
%alloca = alloca i32, i32 %idx, align 2, addrspace(5)
store volatile i32 666, ptr addrspace(5) %alloca
ret void
}
-; CHECK: in function test_dynamic_stackalloc{{.*}}: unsupported dynamic alloca
-; CHECK: in function test_dynamic_stackalloc{{.*}}: unsupported dynamic alloca
-; CHECK: in function test_dynamic_stackalloc{{.*}}: unsupported dynamic alloca
define void @test_dynamic_stackalloc_device_multiple_allocas(i32 %n, i32 %m) {
+; DYN-LABEL: test_dynamic_stackalloc_device_multiple_allocas:
+; DYN: ; %bb.0: ; %entry
+; DYN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; DYN-NEXT: s_mov_b32 s13, s33
+; DYN-NEXT: s_add_i32 s33, s32, 0xfc0
+; DYN-NEXT: s_mov_b32 s8, 0
+; DYN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; DYN-NEXT: s_and_b32 s33, s33, 0xfffff000
+; DYN-NEXT: s_addk_i32 s32, 0x3000
+; DYN-NEXT: s_and_saveexec_b64 s[4:5], vcc
+; DYN-NEXT: s_cbranch_execz .LBB14_6
+; DYN-NEXT: ; %bb.1: ; %bb.0
+; DYN-NEXT: v_lshl_add_u32 v1, v1, 2, 15
+; DYN-NEXT: v_and_b32_e32 v1, -16, v1
+; DYN-NEXT: s_mov_b64 s[6:7], exec
+; DYN-NEXT: s_mov_b32 s10, 0
+; DYN-NEXT: .LBB14_2: ; =>This Inner Loop Header: Depth=1
+; DYN-NEXT: s_ff1_i32_b64 s9, s[6:7]
+; DYN-NEXT: v_readlane_b32 s11, v1, s9
+; DYN-NEXT: s_bitset0_b64 s[6:7], s9
+; DYN-NEXT: s_max_u32 s10, s10, s11
+; DYN-NEXT: s_cmp_lg_u64 s[6:7], 0
+; DYN-NEXT: s_cbranch_scc1 .LBB14_2
+; DYN-NEXT: ; %bb.3:
+; DYN-NEXT: s_add_i32 s6, s32, 0xfff
+; DYN-NEXT: s_and_b32 s9, s6, 0xfffff000
+; DYN-NEXT: v_mov_b32_e32 v1, s9
+; DYN-NEXT: v_lshl_add_u32 v1, s10, 6, v1
+; DYN-NEXT: v_readfirstlane_b32 s32, v1
+; DYN-NEXT: v_and_b32_e32 v1, 0x3ff, v31
+; DYN-NEXT: v_lshl_add_u32 v1, v1, 2, 15
+; DYN-NEXT: v_and_b32_e32 v1, 0x1ff0, v1
+; DYN-NEXT: s_mov_b64 s[6:7], exec
+; DYN-NEXT: s_mov_b32 s10, 0
+; DYN-NEXT: .LBB14_4: ; =>This Inner Loop Header: Depth=1
+; DYN-NEXT: s_ff1_i32_b64 s11, s[6:7]
+; DYN-NEXT: v_readlane_b32 s12, v1, s11
+; DYN-NEXT: s_bitset0_b64 s[6:7], s11
+; DYN-NEXT: s_max_u32 s10, s10, s12
+; DYN-NEXT: s_cmp_lg_u64 s[6:7], 0
+; DYN-NEXT: s_cbranch_scc1 .LBB14_4
+; DYN-NEXT: ; %bb.5:
+; DYN-NEXT: s_mov_b32 s6, s32
+; DYN-NEXT: v_mov_b32_e32 v1, s6
+; DYN-NEXT: v_lshl_add_u32 v1, s10, 6, v1
+; DYN-NEXT: v_readfirstlane_b32 s32, v1
+; DYN-NEXT: v_mov_b32_e32 v1, 3
+; DYN-NEXT: v_mov_b32_e32 v2, s9
+; DYN-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; DYN-NEXT: s_waitcnt vmcnt(0)
+; DYN-NEXT: v_mov_b32_e32 v1, 4
+; DYN-NEXT: buffer_store_dword v1, off, s[0:3], s6
+; DYN-NEXT: s_waitcnt vmcnt(0)
+; DYN-NEXT: .LBB14_6: ; %bb.1
+; DYN-NEXT: s_or_b64 exec, exec, s[4:5]
+; DYN-NEXT: v_lshl_add_u32 v0, v0, 2, 15
+; DYN-NEXT: v_mov_b32_e32 v1, 2
+; DYN-NEXT: v_and_b32_e32 v0, -16, v0
+; DYN-NEXT: s_mov_b64 s[4:5], exec
+; DYN-NEXT: .LBB14_7: ; =>This Inner Loop Header: Depth=1
+; DYN-NEXT: s_ff1_i32_b64 s6, s[4:5]
+; DYN-NEXT: v_readlane_b32 s7, v0, s6
+; DYN-NEXT: s_bitset0_b64 s[4:5], s6
+; DYN-NEXT: s_max_u32 s8, s8, s7
+; DYN-NEXT: s_cmp_lg_u64 s[4:5], 0
+; DYN-NEXT: s_cbranch_scc1 .LBB14_7
+; DYN-NEXT: ; %bb.8:
+; DYN-NEXT: s_mov_b32 s4, s32
+; DYN-NEXT: v_mov_b32_e32 v0, s4
+; DYN-NEXT: v_lshl_add_u32 v0, s8, 6, v0
+; DYN-NEXT: v_readfirstlane_b32 s32, v0
+; DYN-NEXT: v_mov_b32_e32 v0, 1
+; DYN-NEXT: buffer_store_dword v0, off, s[0:3], s33
+; DYN-NEXT: s_waitcnt vmcnt(0)
+; DYN-NEXT: buffer_store_dword v1, off, s[0:3], s4
+; DYN-NEXT: s_waitcnt vmcnt(0)
+; DYN-NEXT: s_addk_i32 s32, 0xd000
+; DYN-NEXT: s_mov_b32 s33, s13
+; DYN-NEXT: s_setpc_b64 s[30:31]
entry:
%cond = icmp eq i32 %n, 0
%alloca1 = alloca i32, i32 8, addrspace(5)
@@ -171,10 +673,71 @@ bb.1:
ret void
}
-; CHECK: in function test_dynamic_stackalloc{{.*}}: unsupported dynamic alloca
-; CHECK: in function test_dynamic_stackalloc{{.*}}: unsupported dynamic alloca
define void @test_dynamic_stackalloc_device_control_flow(i32 %n, i32 %m) {
+; DYN-LABEL: test_dynamic_stackalloc_device_control_flow:
+; DYN: ; %bb.0: ; %entry
+; DYN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; DYN-NEXT: s_mov_b32 s11, s33
+; DYN-NEXT: s_add_i32 s33, s32, 0xfc0
+; DYN-NEXT: s_mov_b32 s8, 0
+; DYN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; DYN-NEXT: s_and_b32 s33, s33, 0xfffff000
+; DYN-NEXT: s_addk_i32 s32, 0x2000
+; DYN-NEXT: s_and_saveexec_b64 s[4:5], vcc
+; DYN-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; DYN-NEXT: s_cbranch_execz .LBB15_4
+; DYN-NEXT: ; %bb.1: ; %bb.1
+; DYN-NEXT: v_lshl_add_u32 v1, v1, 2, 15
+; DYN-NEXT: v_mov_b32_e32 v0, 2
+; DYN-NEXT: v_and_b32_e32 v1, -16, v1
+; DYN-NEXT: s_mov_b64 s[6:7], exec
+; DYN-NEXT: .LBB15_2: ; =>This Inner Loop Header: Depth=1
+; DYN-NEXT: s_ff1_i32_b64 s9, s[6:7]
+; DYN-NEXT: v_readlane_b32 s10, v1, s9
+; DYN-NEXT: s_bitset0_b64 s[6:7], s9
+; DYN-NEXT: s_max_u32 s8, s8, s10
+; DYN-NEXT: s_cmp_lg_u64 s[6:7], 0
+; DYN-NEXT: s_cbranch_scc1 .LBB15_2
+; DYN-NEXT: ; %bb.3:
+; DYN-NEXT: s_add_i32 s6, s32, 0xfff
+; DYN-NEXT: s_and_b32 s6, s6, 0xfffff000
+; DYN-NEXT: v_mov_b32_e32 v1, s6
+; DYN-NEXT: v_lshl_add_u32 v2, s8, 6, v1
+; DYN-NEXT: v_readfirstlane_b32 s32, v2
+; DYN-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen
+; DYN-NEXT: s_waitcnt vmcnt(0)
+; DYN-NEXT: ; implicit-def: $vgpr31
+; DYN-NEXT: .LBB15_4: ; %Flow
+; DYN-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; DYN-NEXT: s_cbranch_execz .LBB15_8
+; DYN-NEXT: ; %bb.5: ; %bb.0
+; DYN-NEXT: v_and_b32_e32 v0, 0x3ff, v31
+; DYN-NEXT: v_lshl_add_u32 v0, v0, 2, 15
+; DYN-NEXT: v_and_b32_e32 v0, 0x1ff0, v0
+; DYN-NEXT: s_mov_b64 s[6:7], exec
+; DYN-NEXT: s_mov_b32 s8, 0
+; DYN-NEXT: .LBB15_6: ; =>This Inner Loop Header: Depth=1
+; DYN-NEXT: s_ff1_i32_b64 s9, s[6:7]
+; DYN-NEXT: v_readlane_b32 s10, v0, s9
+; DYN-NEXT: s_bitset0_b64 s[6:7], s9
+; DYN-NEXT: s_max_u32 s8, s8, s10
+; DYN-NEXT: s_cmp_lg_u64 s[6:7], 0
+; DYN-NEXT: s_cbranch_scc1 .LBB15_6
+; DYN-NEXT: ; %bb.7:
+; DYN-NEXT: s_mov_b32 s6, s32
+; DYN-NEXT: v_mov_b32_e32 v0, s6
+; DYN-NEXT: v_lshl_add_u32 v0, s8, 6, v0
+; DYN-NEXT: v_readfirstlane_b32 s32, v0
+; DYN-NEXT: v_mov_b32_e32 v0, 1
+; DYN-NEXT: buffer_store_dword v0, off, s[0:3], s6
+; DYN-NEXT: s_waitcnt vmcnt(0)
+; DYN-NEXT: .LBB15_8: ; %bb.2
+; DYN-NEXT: s_or_b64 exec, exec, s[4:5]
+; DYN-NEXT: s_addk_i32 s32, 0xe000
+; DYN-NEXT: s_mov_b32 s33, s11
+; DYN-NEXT: s_waitcnt vmcnt(0)
+; DYN-NEXT: s_setpc_b64 s[30:31]
entry:
%cond = icmp eq i32 %n, 0
br i1 %cond, label %bb.0, label %bb.1
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