[llvm] [MachinePipeliner] Use `RegisterClassInfo::getRegPressureSetLimit` (PR #119827)

[Pengcheng Wang via llvm-commits]

wangpc-pp wrote:

> isFixedRegister

Sorry, I was thinking that I may have solved your problem.
I think fixed registers are subset of reserved registers.
For AArch64, fixed registers are:
```cpp
bool AArch64GenRegisterInfo::
isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
  return
      AArch64::CCRRegClass.contains(PhysReg) ||
      AArch64::FIXED_REGSRegClass.contains(PhysReg) ||
      false;
}
```
```rust
// Condition code regclass.
def CCR : RegisterClass<"AArch64", [i32], 32, (add NZCV)> {
  let CopyCost = -1;  // Don't allow copying of status registers.

  // CCR is not allocatable.
  let isAllocatable = 0;
}

def FIXED_REGS : RegisterClass<"AArch64", [i64], 64, (add FP, SP, VG, FFR)>;
def FixedRegisters : RegisterCategory<[CCR, FIXED_REGS]>;
```
Reserved registers are:
https://github.com/llvm/llvm-project/blob/93743ee566694d2fcafa3243c03330e86bf9c806/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp#L426-L518

So, all fixed registers are also reserved registers.

I created https://github.com/llvm/llvm-project/pull/120694 to skip reserved registers, please have a look. :-)

https://github.com/llvm/llvm-project/pull/119827