[llvm] [RISCV] Swap the order of SEWGreaterThanOrEqualAndLessThan64 and SEWGreaterThanOrEqual. (PR #120649)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Dec 19 20:42:27 PST 2024
https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/120649
>From e34cc17e57065c33b56ae6a3101444beaa6908aa Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Thu, 19 Dec 2024 20:35:08 -0800
Subject: [PATCH 1/4] Add test case
---
.../RISCV/rvv/vsetvli-insert-zve64f.mir | 39 +++++++++++++++++++
1 file changed, 39 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-zve64f.mir
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-zve64f.mir b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-zve64f.mir
new file mode 100644
index 00000000000000..7768eae0f9e27b
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-zve64f.mir
@@ -0,0 +1,39 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc %s -mtriple=riscv64 -mattr=+zve64f -run-pass=riscv-insert-vsetvli -o - | FileCheck %s
+
+---
+name: spam
+tracksRegLiveness: true
+noPhis: true
+isSSA: false
+body: |
+ bb.0.entry:
+ liveins: $x10, $x11, $x12, $f10_f
+
+ ; CHECK-LABEL: name: spam
+ ; CHECK: liveins: $x10, $x11, $x12, $f10_f
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x12
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x10
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr32 = COPY $f10_f
+ ; CHECK-NEXT: $x0 = PseudoVSETIVLI 1, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
+ ; CHECK-NEXT: renamable $v10 = PseudoVFMV_S_FPR32 undef renamable $v10, [[COPY3]], 8, 5 /* e32 */, implicit $vl, implicit $vtype
+ ; CHECK-NEXT: renamable $v11 = PseudoVMV_S_X undef renamable $v11, [[COPY2]], 8, 5 /* e32 */, implicit $vl, implicit $vtype
+ ; CHECK-NEXT: renamable $v8 = PseudoVLE64_V_M1 undef renamable $v8, [[COPY1]], 1, 6 /* e64 */, 2 /* tu, ma */, implicit $vl, implicit $vtype :: (load unknown-size, align 8)
+ ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 8, 208 /* e32, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
+ ; CHECK-NEXT: renamable $v9 = PseudoVLE32_V_M1 undef renamable $v9, [[COPY]], 8, 5 /* e32 */, 2 /* tu, ma */, implicit $vl, implicit $vtype :: (load unknown-size, align 4)
+ ; CHECK-NEXT: INLINEASM &"# use $0 $1 $2 $3", 1 /* sideeffect attdialect */, 3145737 /* reguse:VR */, killed renamable $v10, 3145737 /* reguse:VR */, killed renamable $v11, 3145737 /* reguse:VR */, killed renamable $v8, 3145737 /* reguse:VR */, killed renamable $v9
+ ; CHECK-NEXT: PseudoRET
+ %3:gpr = COPY $x12
+ %2:gpr = COPY $x11
+ %1:gpr = COPY $x10
+ %0:fpr32 = COPY $f10_f
+ renamable $v10 = PseudoVFMV_S_FPR32 undef renamable $v10, %0, 8, 5 /* e32 */
+ renamable $v11 = PseudoVMV_S_X undef renamable $v11, %1, 8, 5 /* e32 */
+ renamable $v8 = PseudoVLE64_V_M1 undef renamable $v8, %2, 1, 6 /* e64 */, 2 /* tu, ma */ :: (load unknown-size, align 8)
+ renamable $v9 = PseudoVLE32_V_M1 undef renamable $v9, %3, 8, 5 /* e32 */, 2 /* tu, ma */ :: (load unknown-size, align 4)
+ INLINEASM &"# use $0 $1 $2 $3", 1 /* sideeffect attdialect */, 3145737 /* reguse:VR */, killed renamable $v10, 3145737 /* reguse:VR */, killed renamable $v11, 3145737 /* reguse:VR */, killed renamable $v8, 3145737 /* reguse:VR */, killed renamable $v9
+ PseudoRET
+
+...
>From d1dfdc6bf8d839edfdde4b226784a84f1b47a0e8 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Thu, 19 Dec 2024 15:36:28 -0800
Subject: [PATCH 2/4] [RISCV] Swap the order of
SEWGreaterThanOrEqualAndLessThan64 and SEWGreaterThanOrEqual.
SEWGreaterThanOrEqualAndLessThan64 is a stricter constraint so
it should have a higher value than SEWGreaterThanOrEqual.
Found by our random test generator. I don't have a test case yet.
---
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index 49c2bc90c085ab..55f2742edf38e3 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -219,12 +219,12 @@ struct DemandedFields {
// What properties of SEW we need to preserve.
enum : uint8_t {
SEWEqual = 3, // The exact value of SEW needs to be preserved.
- SEWGreaterThanOrEqual = 2, // SEW can be changed as long as it's greater
- // than or equal to the original value.
SEWGreaterThanOrEqualAndLessThan64 =
- 1, // SEW can be changed as long as it's greater
+ 2, // SEW can be changed as long as it's greater
// than or equal to the original value, but must be less
// than 64.
+ SEWGreaterThanOrEqual = 1, // SEW can be changed as long as it's greater
+ // than or equal to the original value.
SEWNone = 0 // We don't need to preserve SEW at all.
} SEW = SEWNone;
enum : uint8_t {
>From 4b05735e0784f7ad4b817f2e20ee03bcc1ede03b Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Thu, 19 Dec 2024 15:48:37 -0800
Subject: [PATCH 3/4] fixup! clang-format
---
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index 55f2742edf38e3..75985832594d45 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -218,14 +218,14 @@ struct DemandedFields {
bool VLZeroness = false;
// What properties of SEW we need to preserve.
enum : uint8_t {
- SEWEqual = 3, // The exact value of SEW needs to be preserved.
+ SEWEqual = 3, // The exact value of SEW needs to be preserved.
SEWGreaterThanOrEqualAndLessThan64 =
- 2, // SEW can be changed as long as it's greater
- // than or equal to the original value, but must be less
- // than 64.
+ 2, // SEW can be changed as long as it's greater
+ // than or equal to the original value, but must be less
+ // than 64.
SEWGreaterThanOrEqual = 1, // SEW can be changed as long as it's greater
// than or equal to the original value.
- SEWNone = 0 // We don't need to preserve SEW at all.
+ SEWNone = 0 // We don't need to preserve SEW at all.
} SEW = SEWNone;
enum : uint8_t {
LMULEqual = 2, // The exact value of LMUL needs to be preserved.
>From 1f65f1282ecf228af94ac5edab3fe05f061924cd Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Thu, 19 Dec 2024 20:36:45 -0800
Subject: [PATCH 4/4] Update test.
---
llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-zve64f.mir | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-zve64f.mir b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-zve64f.mir
index 7768eae0f9e27b..f65bba1b7b9c7e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-zve64f.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-zve64f.mir
@@ -17,9 +17,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr32 = COPY $f10_f
- ; CHECK-NEXT: $x0 = PseudoVSETIVLI 1, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
+ ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 8, 208 /* e32, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: renamable $v10 = PseudoVFMV_S_FPR32 undef renamable $v10, [[COPY3]], 8, 5 /* e32 */, implicit $vl, implicit $vtype
; CHECK-NEXT: renamable $v11 = PseudoVMV_S_X undef renamable $v11, [[COPY2]], 8, 5 /* e32 */, implicit $vl, implicit $vtype
+ ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 1, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: renamable $v8 = PseudoVLE64_V_M1 undef renamable $v8, [[COPY1]], 1, 6 /* e64 */, 2 /* tu, ma */, implicit $vl, implicit $vtype :: (load unknown-size, align 8)
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 8, 208 /* e32, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: renamable $v9 = PseudoVLE32_V_M1 undef renamable $v9, [[COPY]], 8, 5 /* e32 */, 2 /* tu, ma */, implicit $vl, implicit $vtype :: (load unknown-size, align 4)
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