[llvm] ebb5f1a - [AArch64][GlobalISel] Fix crash when selecting an anyextending FP load.

[Amara Emerson via llvm-commits]

Author: Amara Emerson
Date: 2024-12-19T20:11:30-08:00
New Revision: ebb5f1a4e5f2f150c60302a9374b3ae1b66e2028

URL: https://github.com/llvm/llvm-project/commit/ebb5f1a4e5f2f150c60302a9374b3ae1b66e2028
DIFF: https://github.com/llvm/llvm-project/commit/ebb5f1a4e5f2f150c60302a9374b3ae1b66e2028.diff

LOG: [AArch64][GlobalISel] Fix crash when selecting an anyextending FP load.

We split anyext FP loads back into a regular load + extend, but when we do that
we need to ensure that some state about the instruction is updated to correctly
reflect the new reality.

rdar://141660282

Added: 
    llvm/test/CodeGen/AArch64/GlobalISel/select-fp-anyext-crash.ll

Modified: 
    llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index 5000078928a1d2..07f03644336cdd 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -3055,8 +3055,8 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
 #endif
 
     const Register ValReg = LdSt.getReg(0);
-    const LLT ValTy = MRI.getType(ValReg);
     const RegisterBank &RB = *RBI.getRegBank(ValReg, MRI, TRI);
+    LLT ValTy = MRI.getType(ValReg);
 
     // The code below doesn't support truncating stores, so we need to split it
     // again.
@@ -3096,6 +3096,7 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
         auto SubRegRC = getRegClassForTypeOnBank(MRI.getType(OldDst), RB);
         RBI.constrainGenericRegister(OldDst, *SubRegRC, MRI);
         MIB.setInstr(LdSt);
+        ValTy = MemTy; // This is no longer an extending load.
       }
     }
 

diff  --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-fp-anyext-crash.ll b/llvm/test/CodeGen/AArch64/GlobalISel/select-fp-anyext-crash.ll
new file mode 100644
index 00000000000000..7af5b3d801e0c5
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-fp-anyext-crash.ll
@@ -0,0 +1,42 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -O0 -o - %s | FileCheck %s
+target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128-Fn32"
+target triple = "arm64e-apple-macosx10.15.0"
+
+; Check we don't crash here when selecting an anyextending FP load.
+
+define i32 @test() {
+; CHECK-LABEL: test:
+; CHECK:       ; %bb.0: ; %entry
+; CHECK-NEXT:    sub sp, sp, #80
+; CHECK-NEXT:    stp x29, x30, [sp, #64] ; 16-byte Folded Spill
+; CHECK-NEXT:    .cfi_def_cfa_offset 80
+; CHECK-NEXT:    .cfi_offset w30, -8
+; CHECK-NEXT:    .cfi_offset w29, -16
+; CHECK-NEXT:    mov x8, #0 ; =0x0
+; CHECK-NEXT:    ldr s0, [x8]
+; CHECK-NEXT:    ; kill: def $d0 killed $s0
+; CHECK-NEXT:    mov x8, sp
+; CHECK-NEXT:    mov w9, #0 ; =0x0
+; CHECK-NEXT:    str w9, [sp, #60] ; 4-byte Folded Spill
+; CHECK-NEXT:    str xzr, [x8]
+; CHECK-NEXT:    str xzr, [x8, #8]
+; CHECK-NEXT:    str xzr, [x8, #16]
+; CHECK-NEXT:    str xzr, [x8, #24]
+; CHECK-NEXT:    str d0, [x8, #32]
+; CHECK-NEXT:    str xzr, [x8, #40]
+; CHECK-NEXT:    mov x8, #0 ; =0x0
+; CHECK-NEXT:    mov x0, x8
+; CHECK-NEXT:    blr x8
+; CHECK-NEXT:    ldr w0, [sp, #60] ; 4-byte Folded Reload
+; CHECK-NEXT:    ldp x29, x30, [sp, #64] ; 16-byte Folded Reload
+; CHECK-NEXT:    add sp, sp, #80
+; CHECK-NEXT:    ret
+entry:
+  %0 = inttoptr i64 0 to ptr
+  %1 = load i32, ptr %0, align 4
+  %call86 = call i32 (ptr, ...) null(ptr null, i32 0, i32 0, i32 0, i32 0, i32 %1, i32 0)
+  %2 = load float, ptr %0, align 4
+  ret i32 0
+}
+