[llvm] IR/Verifier: Allow vector type in atomic load and store (PR #120384)

[Nikita Popov via llvm-commits]

nikic wrote:

Seeing the rest of the patch series, I'm a bit confused on what the semantics atomic vector load/store are actually supposed to me. My initial assumption was that `load atomic <2 x i32>` is, in terms of semantics, equivalent to `load atomic i64` with appropriate bitcasts. But it looks like you actually want it to be equivalent to two `load atomic i32` instructions that then get assembled into a vector. That is, you do not guarantee that all components of the vector will be loaded atomically, only that each individual component is loaded atomically.

Either way, this needs to be clearly spelled out in LangRef.

https://github.com/llvm/llvm-project/pull/120384