[llvm] [RISC-V] Fix incorrect epilogue_begin (PR #120623)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Dec 19 11:10:00 PST 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Venkata Ramanaiah Nalamothu (RamNalamothu)
<details>
<summary>Changes</summary>
---
Patch is 143.26 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/120623.diff
61 Files Affected:
- (modified) llvm/include/llvm/CodeGen/TargetInstrInfo.h (+16-14)
- (modified) llvm/lib/Target/AArch64/AArch64InstrInfo.cpp (+6-7)
- (modified) llvm/lib/Target/AArch64/AArch64InstrInfo.h (+11-12)
- (modified) llvm/lib/Target/AMDGPU/SIInstrInfo.cpp (+4-2)
- (modified) llvm/lib/Target/AMDGPU/SIInstrInfo.h (+11-12)
- (modified) llvm/lib/Target/ARC/ARCInstrInfo.cpp (+4-2)
- (modified) llvm/lib/Target/ARC/ARCInstrInfo.h (+11-12)
- (modified) llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp (+6-7)
- (modified) llvm/lib/Target/ARM/ARMBaseInstrInfo.h (+11-12)
- (modified) llvm/lib/Target/ARM/Thumb1InstrInfo.cpp (+6-7)
- (modified) llvm/lib/Target/ARM/Thumb1InstrInfo.h (+11-12)
- (modified) llvm/lib/Target/ARM/Thumb2InstrInfo.cpp (+6-7)
- (modified) llvm/lib/Target/ARM/Thumb2InstrInfo.h (+11-12)
- (modified) llvm/lib/Target/AVR/AVRInstrInfo.cpp (+4-2)
- (modified) llvm/lib/Target/AVR/AVRInstrInfo.h (+10-11)
- (modified) llvm/lib/Target/BPF/BPFInstrInfo.cpp (+6-7)
- (modified) llvm/lib/Target/BPF/BPFInstrInfo.h (+10-11)
- (modified) llvm/lib/Target/CSKY/CSKYInstrInfo.cpp (+6-7)
- (modified) llvm/lib/Target/CSKY/CSKYInstrInfo.h (+11-12)
- (modified) llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp (+6-7)
- (modified) llvm/lib/Target/Hexagon/HexagonInstrInfo.h (+10-11)
- (modified) llvm/lib/Target/Lanai/LanaiInstrInfo.cpp (+4-2)
- (modified) llvm/lib/Target/Lanai/LanaiInstrInfo.h (+13-13)
- (modified) llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp (+6-7)
- (modified) llvm/lib/Target/LoongArch/LoongArchInstrInfo.h (+10-11)
- (modified) llvm/lib/Target/M68k/M68kInstrInfo.cpp (+4-2)
- (modified) llvm/lib/Target/M68k/M68kInstrInfo.h (+11-12)
- (modified) llvm/lib/Target/MSP430/MSP430InstrInfo.cpp (+6-7)
- (modified) llvm/lib/Target/MSP430/MSP430InstrInfo.h (+10-11)
- (modified) llvm/lib/Target/Mips/Mips16InstrInfo.cpp (+6-7)
- (modified) llvm/lib/Target/Mips/Mips16InstrInfo.h (+11-13)
- (modified) llvm/lib/Target/Mips/MipsInstrInfo.h (+24-26)
- (modified) llvm/lib/Target/Mips/MipsSEInstrInfo.cpp (+11-9)
- (modified) llvm/lib/Target/Mips/MipsSEInstrInfo.h (+11-13)
- (modified) llvm/lib/Target/NVPTX/NVPTXInstrInfo.h (+10-11)
- (modified) llvm/lib/Target/PowerPC/PPCInstrInfo.cpp (+6-7)
- (modified) llvm/lib/Target/PowerPC/PPCInstrInfo.h (+10-11)
- (modified) llvm/lib/Target/RISCV/RISCVFrameLowering.cpp (+26-14)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.cpp (+18-13)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.h (+11-12)
- (modified) llvm/lib/Target/Sparc/SparcInstrInfo.cpp (+6-7)
- (modified) llvm/lib/Target/Sparc/SparcInstrInfo.h (+11-12)
- (modified) llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp (+6-7)
- (modified) llvm/lib/Target/SystemZ/SystemZInstrInfo.h (+10-11)
- (modified) llvm/lib/Target/VE/VEInstrInfo.cpp (+6-7)
- (modified) llvm/lib/Target/VE/VEInstrInfo.h (+11-12)
- (modified) llvm/lib/Target/X86/X86InstrInfo.cpp (+6-7)
- (modified) llvm/lib/Target/X86/X86InstrInfo.h (+11-12)
- (modified) llvm/lib/Target/XCore/XCoreInstrInfo.cpp (+4-2)
- (modified) llvm/lib/Target/XCore/XCoreInstrInfo.h (+11-12)
- (modified) llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp (+6-7)
- (modified) llvm/lib/Target/Xtensa/XtensaInstrInfo.h (+11-12)
- (added) llvm/test/CodeGen/RISCV/debug-line.ll (+50)
- (modified) llvm/test/CodeGen/RISCV/kcfi-mir.ll (+2-2)
- (modified) llvm/test/CodeGen/RISCV/live-sp.mir (+2-2)
- (modified) llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir (+4-4)
- (modified) llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir (+24-24)
- (modified) llvm/test/CodeGen/RISCV/stack-inst-compress.mir (+24-24)
- (modified) llvm/test/CodeGen/RISCV/zcmp-cm-popretz.mir (+16-16)
- (modified) llvm/test/CodeGen/RISCV/zcmp-cm-push-pop.mir (+52-52)
- (modified) llvm/test/DebugInfo/RISCV/dwarf-riscv-relocs.ll (+1-1)
``````````diff
diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
index 408adcd330b846..9b8fc2ef46afd7 100644
--- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -1138,13 +1138,14 @@ class TargetInstrInfo : public MCInstrInfo {
/// register, \p VReg is the register being assigned. This additional register
/// argument is needed for certain targets when invoked from RegAllocFast to
/// map the spilled physical register to its virtual register. A null register
- /// can be passed elsewhere.
- virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI,
- Register SrcReg, bool isKill, int FrameIndex,
- const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI,
- Register VReg) const {
+ /// can be passed elsewhere. The \p Flags is used to set appropriate machine
+ /// flags on the spill instruction e.g. FrameSetup flag on a callee saved
+ /// register spill instruction, part of prologue, during the frame lowering.
+ virtual void storeRegToStackSlot(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg,
+ bool isKill, int FrameIndex, const TargetRegisterClass *RC,
+ const TargetRegisterInfo *TRI, Register VReg,
+ MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const {
llvm_unreachable("Target didn't implement "
"TargetInstrInfo::storeRegToStackSlot!");
}
@@ -1156,13 +1157,14 @@ class TargetInstrInfo : public MCInstrInfo {
/// register, \p VReg is the register being assigned. This additional register
/// argument is needed for certain targets when invoked from RegAllocFast to
/// map the loaded physical register to its virtual register. A null register
- /// can be passed elsewhere.
- virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI,
- Register DestReg, int FrameIndex,
- const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI,
- Register VReg) const {
+ /// can be passed elsewhere. The \p Flags is used to set appropriate machine
+ /// flags on the spill instruction e.g. FrameDestroy flag on a callee saved
+ /// register reload instruction, part of epilogue, during the frame lowering.
+ virtual void loadRegFromStackSlot(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg,
+ int FrameIndex, const TargetRegisterClass *RC,
+ const TargetRegisterInfo *TRI, Register VReg,
+ MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const {
llvm_unreachable("Target didn't implement "
"TargetInstrInfo::loadRegFromStackSlot!");
}
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index fd24e49f948a20..3af891b95fe3d3 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -5278,7 +5278,8 @@ void AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
Register SrcReg, bool isKill, int FI,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI,
- Register VReg) const {
+ Register VReg,
+ MachineInstr::MIFlag Flags) const {
MachineFunction &MF = *MBB.getParent();
MachineFrameInfo &MFI = MF.getFrameInfo();
@@ -5445,12 +5446,10 @@ static void loadRegPairFromStackSlot(const TargetRegisterInfo &TRI,
.addMemOperand(MMO);
}
-void AArch64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
- Register DestReg, int FI,
- const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI,
- Register VReg) const {
+void AArch64InstrInfo::loadRegFromStackSlot(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg,
+ int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
+ Register VReg, MachineInstr::MIFlag Flags) const {
MachineFunction &MF = *MBB.getParent();
MachineFrameInfo &MFI = MF.getFrameInfo();
MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(MF, FI);
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.h b/llvm/lib/Target/AArch64/AArch64InstrInfo.h
index e37f70f7d985de..9a0034223ab9ba 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.h
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.h
@@ -347,18 +347,17 @@ class AArch64InstrInfo final : public AArch64GenInstrInfo {
bool KillSrc, bool RenamableDest = false,
bool RenamableSrc = false) const override;
- void storeRegToStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI, Register SrcReg,
- bool isKill, int FrameIndex,
- const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI,
- Register VReg) const override;
-
- void loadRegFromStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI, Register DestReg,
- int FrameIndex, const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI,
- Register VReg) const override;
+ void storeRegToStackSlot(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg,
+ bool isKill, int FrameIndex, const TargetRegisterClass *RC,
+ const TargetRegisterInfo *TRI, Register VReg,
+ MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
+
+ void loadRegFromStackSlot(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ Register DestReg, int FrameIndex, const TargetRegisterClass *RC,
+ const TargetRegisterInfo *TRI, Register VReg,
+ MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
// This tells target independent code that it is okay to pass instructions
// with subreg operands to foldMemoryOperandImpl.
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index f97ea40caa6704..8234e7d0af2529 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -1724,7 +1724,8 @@ static unsigned getVectorRegSpillSaveOpcode(Register Reg,
void SIInstrInfo::storeRegToStackSlot(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg,
bool isKill, int FrameIndex, const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI, Register VReg) const {
+ const TargetRegisterInfo *TRI, Register VReg,
+ MachineInstr::MIFlag Flags) const {
MachineFunction *MF = MBB.getParent();
SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
MachineFrameInfo &FrameInfo = MF->getFrameInfo();
@@ -1951,7 +1952,8 @@ void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
Register DestReg, int FrameIndex,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI,
- Register VReg) const {
+ Register VReg,
+ MachineInstr::MIFlag Flags) const {
MachineFunction *MF = MBB.getParent();
SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
MachineFrameInfo &FrameInfo = MF->getFrameInfo();
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index 8f9ca6141816d4..71a24b6061a698 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -278,18 +278,17 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
MachineBasicBlock::iterator I, const DebugLoc &DL,
Register SrcReg, int Value) const;
- void storeRegToStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI, Register SrcReg,
- bool isKill, int FrameIndex,
- const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI,
- Register VReg) const override;
-
- void loadRegFromStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI, Register DestReg,
- int FrameIndex, const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI,
- Register VReg) const override;
+ void storeRegToStackSlot(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg,
+ bool isKill, int FrameIndex, const TargetRegisterClass *RC,
+ const TargetRegisterInfo *TRI, Register VReg,
+ MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
+
+ void loadRegFromStackSlot(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg,
+ int FrameIndex, const TargetRegisterClass *RC,
+ const TargetRegisterInfo *TRI, Register VReg,
+ MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
bool expandPostRAPseudo(MachineInstr &MI) const override;
diff --git a/llvm/lib/Target/ARC/ARCInstrInfo.cpp b/llvm/lib/Target/ARC/ARCInstrInfo.cpp
index 78db68fca3050a..aa30c8a2a96daf 100644
--- a/llvm/lib/Target/ARC/ARCInstrInfo.cpp
+++ b/llvm/lib/Target/ARC/ARCInstrInfo.cpp
@@ -294,7 +294,8 @@ void ARCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
void ARCInstrInfo::storeRegToStackSlot(
MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register SrcReg,
bool IsKill, int FrameIndex, const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI, Register VReg) const {
+ const TargetRegisterInfo *TRI, Register VReg,
+ MachineInstr::MIFlag Flags) const {
DebugLoc DL = MBB.findDebugLoc(I);
MachineFunction &MF = *MBB.getParent();
MachineFrameInfo &MFI = MF.getFrameInfo();
@@ -323,7 +324,8 @@ void ARCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
Register DestReg, int FrameIndex,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI,
- Register VReg) const {
+ Register VReg,
+ MachineInstr::MIFlag Flags) const {
DebugLoc DL = MBB.findDebugLoc(I);
MachineFunction &MF = *MBB.getParent();
MachineFrameInfo &MFI = MF.getFrameInfo();
diff --git a/llvm/lib/Target/ARC/ARCInstrInfo.h b/llvm/lib/Target/ARC/ARCInstrInfo.h
index e25f9902522607..8861b4689925f2 100644
--- a/llvm/lib/Target/ARC/ARCInstrInfo.h
+++ b/llvm/lib/Target/ARC/ARCInstrInfo.h
@@ -68,18 +68,17 @@ class ARCInstrInfo : public ARCGenInstrInfo {
bool KillSrc, bool RenamableDest = false,
bool RenamableSrc = false) const override;
- void storeRegToStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI, Register SrcReg,
- bool IsKill, int FrameIndex,
- const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI,
- Register VReg) const override;
-
- void loadRegFromStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI, Register DestReg,
- int FrameIndex, const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI,
- Register VReg) const override;
+ void storeRegToStackSlot(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg,
+ bool IsKill, int FrameIndex, const TargetRegisterClass *RC,
+ const TargetRegisterInfo *TRI, Register VReg,
+ MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
+
+ void loadRegFromStackSlot(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg,
+ int FrameIndex, const TargetRegisterClass *RC,
+ const TargetRegisterInfo *TRI, Register VReg,
+ MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
bool
reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index e3e2e83fd5c7eb..89abdb11595ab5 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -1118,7 +1118,8 @@ void ARMBaseInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
Register SrcReg, bool isKill, int FI,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI,
- Register VReg) const {
+ Register VReg,
+ MachineInstr::MIFlag Flags) const {
MachineFunction &MF = *MBB.getParent();
MachineFrameInfo &MFI = MF.getFrameInfo();
Align Alignment = MFI.getObjectAlign(FI);
@@ -1379,12 +1380,10 @@ Register ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
return false;
}
-void ARMBaseInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator I,
- Register DestReg, int FI,
- const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI,
- Register VReg) const {
+void ARMBaseInstrInfo::loadRegFromStackSlot(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DestReg,
+ int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
+ Register VReg, MachineInstr::MIFlag Flags) const {
DebugLoc DL;
if (I != MBB.end()) DL = I->getDebugLoc();
MachineFunction &MF = *MBB.getParent();
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
index b6f20e6f99a0a9..afe610a0d9dd73 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
@@ -212,18 +212,17 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
bool KillSrc, bool RenamableDest = false,
bool RenamableSrc = false) const override;
- void storeRegToStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI, Register SrcReg,
- bool isKill, int FrameIndex,
- const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI,
- Register VReg) const override;
-
- void loadRegFromStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI, Register DestReg,
- int FrameIndex, const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI,
- Register VReg) const override;
+ void storeRegToStackSlot(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg,
+ bool isKill, int FrameIndex, const TargetRegisterClass *RC,
+ const TargetRegisterInfo *TRI, Register VReg,
+ MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
+
+ void loadRegFromStackSlot(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ Register DestReg, int FrameIndex, const TargetRegisterClass *RC,
+ const TargetRegisterInfo *TRI, Register VReg,
+ MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
bool expandPostRAPseudo(MachineInstr &MI) const override;
diff --git a/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp b/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
index a38aa3de40d901..cf151e1f8458fb 100644
--- a/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
+++ b/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
@@ -117,7 +117,8 @@ void Thumb1InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
Register SrcReg, bool isKill, int FI,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI,
- Register VReg) const {
+ Register VReg,
+ MachineInstr::MIFlag Flags) const {
assert((RC == &ARM::tGPRRegClass ||
(SrcReg.isPhysical() && isARMLowRegister(SrcReg))) &&
"Unknown regclass!");
@@ -141,12 +142,10 @@ void Thumb1InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
}
}
-void Thumb1InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator I,
- Register DestReg, int FI,
- const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI,
- Register VReg) const {
+void Thumb1InstrInfo::loadRegFromStackSlot(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DestReg,
+ int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
+ Register VReg, MachineInstr::MIFlag Flags) const {
assert((RC->hasSuperClassEq(&ARM::tGPRRegClass) ||
(DestReg.isPhysical() && isARMLowRegister(DestReg))) &&
"Unknown regclass!");
diff --git a/llvm/lib/Target/ARM/Thumb1InstrInfo.h b/llvm/lib/Target/ARM/Thumb1InstrInfo.h
index 84241fb8a9a66b..b9eb58692bab06 100644
--- a/llvm/lib/Target/ARM/Thumb1InstrInfo.h
+++ b/llvm/lib/Target/ARM/Thumb1InstrInfo.h
@@ -41,18 +41,17 @@ class Thumb1InstrInfo : public ARMBaseInstrInfo {
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
bool KillSrc, bool RenamableDest = false,
bool RenamableSrc = false) const override;
- void storeRegToStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI, Register SrcReg,
- bool isKill, int FrameIndex,
- const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI,
- Register VReg) const override;
-
- void loadRegFromStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI, Register DestReg,
- int FrameIndex, const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI,
- Register VReg) const override;
+ void storeRegToStackSlot(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg,
+ bool isKill, int FrameIndex, const TargetRegisterClass *RC,
+ const TargetRegisterInfo *TRI, Register VReg,
+ MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
+
+ void loadRegFromStackSlot(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ Register DestReg, int FrameIndex, const TargetRegisterClass *RC,
+ const TargetRegisterInfo *TRI, Register VReg,
+ MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
bool canCopyGluedNodeDuringSchedule(SDNode *N) c...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/120623
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