[llvm] [AMDGPU] Emit S_CBRANCH_SCC for floating-point conditions. (PR #120588)

[Jay Foad via llvm-commits]

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@@ -2389,13 +2389,15 @@ bool AMDGPUDAGToDAGISel::isCBranchSCC(const SDNode *N) const {
   if (VT == MVT::i32)
     return true;
 
+  const auto *ST = static_cast<const GCNSubtarget *>(Subtarget);
   if (VT == MVT::i64) {
-    const auto *ST = static_cast<const GCNSubtarget *>(Subtarget);
-
     ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
     return (CC == ISD::SETEQ || CC == ISD::SETNE) && ST->hasScalarCompareEq64();
   }
 
+  if ((VT == MVT::f32 || VT == MVT::f64) && ST->hasSALUFloatInsts())
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jayfoad wrote:

SALU float instructions handle f16 and f32 but not f64.

https://github.com/llvm/llvm-project/pull/120588