[llvm] [RISCV] Implement RISCVTTIImpl::getPreferredAddressingMode for HasVendorXCVmem (PR #120533)

[Philipp van Kempen via llvm-commits]

https://github.com/PhilippvK updated https://github.com/llvm/llvm-project/pull/120533

>From 0cc75221d8c79c24950f3ef6b798f92cb9c615bb Mon Sep 17 00:00:00 2001
From: Philipp van Kempen <philipp.van-kempen at tum.de>
Date: Thu, 19 Dec 2024 08:21:08 +0100
Subject: [PATCH 1/2] [RISCV] Implement
 RISCVTTIImpl::getPreferredAddressingMode for HasVendorXCVmem

For a simple matmult kernel this heuristic reduces the length of the critical basic
block from 15 to 20 instructions, resulting in a 20% speedup.
---
 llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp | 9 +++++++++
 llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h   | 3 +++
 2 files changed, 12 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index 49192bd6380223..662649b5b276b1 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -2329,6 +2329,15 @@ unsigned RISCVTTIImpl::getMaximumVF(unsigned ElemWidth, unsigned Opcode) const {
   return std::max<unsigned>(1U, RegWidth.getFixedValue() / ElemWidth);
 }
 
+TTI::AddressingModeKind
+RISCVTTIImpl::getPreferredAddressingMode(const Loop *L,
+                                         ScalarEvolution *SE) const {
+  if (ST->hasVendorXCVmem())
+    return TTI::AMK_PostIndexed;
+
+  return TTI::AMK_None;
+}
+
 bool RISCVTTIImpl::isLSRCostLess(const TargetTransformInfo::LSRCost &C1,
                                  const TargetTransformInfo::LSRCost &C2) {
   // RISC-V specific here are "instruction number 1st priority".
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
index bd90bfed6e2c95..9b364391f0fa47 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
@@ -388,6 +388,9 @@ class RISCVTTIImpl : public BasicTTIImplBase<RISCVTTIImpl> {
     llvm_unreachable("unknown register class");
   }
 
+  TTI::AddressingModeKind getPreferredAddressingMode(const Loop *L,
+                                                     ScalarEvolution *SE) const;
+
   unsigned getRegisterClassForType(bool Vector, Type *Ty = nullptr) const {
     if (Vector)
       return RISCVRegisterClass::VRRC;

>From 19b404cdf581c015dad48172d9f7000ab34dc929 Mon Sep 17 00:00:00 2001
From: Philipp van Kempen <philipp.van-kempen at tum.de>
Date: Thu, 19 Dec 2024 15:27:27 +0100
Subject: [PATCH 2/2] [RISCV] Address PR comment

---
 llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index 662649b5b276b1..b6e13fa7a90094 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -2335,7 +2335,7 @@ RISCVTTIImpl::getPreferredAddressingMode(const Loop *L,
   if (ST->hasVendorXCVmem())
     return TTI::AMK_PostIndexed;
 
-  return TTI::AMK_None;
+  return BasicTTIImplBase::getPreferredAddressingMode(L, SE);
 }
 
 bool RISCVTTIImpl::isLSRCostLess(const TargetTransformInfo::LSRCost &C1,