[llvm] [ARM] Use `RegisterClassInfo::getRegPressureSetLimit` (PR #120377)
Pengcheng Wang via llvm-commits
llvm-commits at lists.llvm.org
Thu Dec 19 04:57:04 PST 2024
https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/120377
>From fc79aef87d46c9281193ed267690c1c95138fdb7 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
Date: Wed, 18 Dec 2024 15:27:32 +0800
Subject: [PATCH 1/2] [ARM] Use `RegisterClassInfo::getRegPressureSetLimit`
`RegisterClassInfo::getRegPressureSetLimit` is a wrapper of
`TargetRegisterInfo::getRegPressureSetLimit` with some logics to
adjust the limit by removing reserved registers.
It seems that we shouldn't use `TargetRegisterInfo::getRegPressureSetLimit`
directly, just like the comment "This limit must be adjusted
dynamically for reserved registers" said.
Separate from https://github.com/llvm/llvm-project/pull/118787
---
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 2 +-
llvm/test/CodeGen/Thumb2/mve-pipelineloops.ll | 75 ++++++++-----------
2 files changed, 33 insertions(+), 44 deletions(-)
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index e6b37dd9161685..891d0c20ebc448 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -6979,7 +6979,7 @@ bool ARMPipelinerLoopInfo::tooMuchRegisterPressure(SwingSchedulerDAG &SSD,
auto &P = RPTracker.getPressure().MaxSetPressure;
for (unsigned I = 0, E = P.size(); I < E; ++I)
- if (P[I] > TRI->getRegPressureSetLimit(*MF, I)) {
+ if (P[I] > RegClassInfo.getRegPressureSetLimit(I)) {
return true;
}
return false;
diff --git a/llvm/test/CodeGen/Thumb2/mve-pipelineloops.ll b/llvm/test/CodeGen/Thumb2/mve-pipelineloops.ll
index 43ed5eefbf4c77..7d7a65640d3705 100644
--- a/llvm/test/CodeGen/Thumb2/mve-pipelineloops.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-pipelineloops.ll
@@ -17,51 +17,40 @@ define void @arm_cmplx_dot_prod_q15(ptr noundef %pSrcA, ptr noundef %pSrcB, i32
; CHECK-NEXT: mov.w r5, #0
; CHECK-NEXT: csel r7, r6, r5, hs
; CHECK-NEXT: add.w lr, r7, #1
-; CHECK-NEXT: mov r4, r5
-; CHECK-NEXT: vldrh.u16 q0, [r0], #32
+; CHECK-NEXT: mov r6, r5
+; CHECK-NEXT: vldrh.u16 q1, [r0], #32
; CHECK-NEXT: movs r7, #0
; CHECK-NEXT: mov r8, r5
-; CHECK-NEXT: vldrh.u16 q1, [r1], #32
-; CHECK-NEXT: vmlsldava.s16 r4, r7, q0, q1
-; CHECK-NEXT: vldrh.u16 q2, [r0, #-16]
-; CHECK-NEXT: vmlaldavax.s16 r8, r5, q0, q1
-; CHECK-NEXT: vldrh.u16 q3, [r1, #-16]
-; CHECK-NEXT: vmlsldava.s16 r4, r7, q2, q3
; CHECK-NEXT: vldrh.u16 q0, [r1], #32
-; CHECK-NEXT: sub.w lr, lr, #1
-; CHECK-NEXT: cmp.w lr, #0
-; CHECK-NEXT: vldrh.u16 q1, [r0], #32
-; CHECK-NEXT: beq .LBB0_3
; CHECK-NEXT: .p2align 2
; CHECK-NEXT: .LBB0_2: @ %while.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: vmlaldavax.s16 r8, r5, q2, q3
-; CHECK-NEXT: vldrh.u16 q3, [r1, #-16]
-; CHECK-NEXT: vmlsldava.s16 r4, r7, q1, q0
+; CHECK-NEXT: vmlsldava.s16 r8, r7, q1, q0
; CHECK-NEXT: vldrh.u16 q2, [r0, #-16]
-; CHECK-NEXT: vmlaldavax.s16 r8, r5, q1, q0
-; CHECK-NEXT: vldrh.u16 q1, [r0], #32
-; CHECK-NEXT: vmlsldava.s16 r4, r7, q2, q3
+; CHECK-NEXT: vmlaldavax.s16 r6, r5, q1, q0
+; CHECK-NEXT: vldrh.u16 q1, [r1, #-16]
+; CHECK-NEXT: vmlsldava.s16 r8, r7, q2, q1
; CHECK-NEXT: vldrh.u16 q0, [r1], #32
+; CHECK-NEXT: vmlaldavax.s16 r6, r5, q2, q1
+; CHECK-NEXT: vldrh.u16 q1, [r0], #32
; CHECK-NEXT: le lr, .LBB0_2
-; CHECK-NEXT: .LBB0_3:
-; CHECK-NEXT: vmlaldavax.s16 r8, r5, q2, q3
-; CHECK-NEXT: movs r6, #14
-; CHECK-NEXT: and.w r2, r6, r2, lsl #1
-; CHECK-NEXT: vmlaldavax.s16 r8, r5, q1, q0
+; CHECK-NEXT: @ %bb.3: @ %do.body
+; CHECK-NEXT: movs r4, #14
+; CHECK-NEXT: and.w r2, r4, r2, lsl #1
+; CHECK-NEXT: vmlaldavax.s16 r6, r5, q1, q0
; CHECK-NEXT: vldrh.u16 q2, [r0, #-16]
-; CHECK-NEXT: vmlsldava.s16 r4, r7, q1, q0
+; CHECK-NEXT: vmlsldava.s16 r8, r7, q1, q0
; CHECK-NEXT: vldrh.u16 q0, [r1, #-16]
-; CHECK-NEXT: vmlaldavax.s16 r8, r5, q2, q0
+; CHECK-NEXT: vmlaldavax.s16 r6, r5, q2, q0
; CHECK-NEXT: vctp.16 r2
-; CHECK-NEXT: vmlsldava.s16 r4, r7, q2, q0
+; CHECK-NEXT: vmlsldava.s16 r8, r7, q2, q0
; CHECK-NEXT: vpst
; CHECK-NEXT: vldrht.u16 q1, [r0]
; CHECK-NEXT: cmp r2, #9
; CHECK-NEXT: vpsttt
; CHECK-NEXT: vldrht.u16 q0, [r1]
-; CHECK-NEXT: vmlsldavat.s16 r4, r7, q1, q0
-; CHECK-NEXT: vmlaldavaxt.s16 r8, r5, q1, q0
+; CHECK-NEXT: vmlsldavat.s16 r8, r7, q1, q0
+; CHECK-NEXT: vmlaldavaxt.s16 r6, r5, q1, q0
; CHECK-NEXT: blo .LBB0_10
; CHECK-NEXT: @ %bb.4: @ %do.body.1
; CHECK-NEXT: subs r2, #8
@@ -69,17 +58,17 @@ define void @arm_cmplx_dot_prod_q15(ptr noundef %pSrcA, ptr noundef %pSrcB, i32
; CHECK-NEXT: vpstttt
; CHECK-NEXT: vldrht.u16 q0, [r0, #16]
; CHECK-NEXT: vldrht.u16 q1, [r1, #16]
-; CHECK-NEXT: vmlsldavat.s16 r4, r7, q0, q1
-; CHECK-NEXT: vmlaldavaxt.s16 r8, r5, q0, q1
+; CHECK-NEXT: vmlsldavat.s16 r8, r7, q0, q1
+; CHECK-NEXT: vmlaldavaxt.s16 r6, r5, q0, q1
; CHECK-NEXT: b .LBB0_10
; CHECK-NEXT: .p2align 2
; CHECK-NEXT: .LBB0_5: @ %if.else
-; CHECK-NEXT: mov.w r4, #0
+; CHECK-NEXT: mov.w r8, #0
; CHECK-NEXT: cbz r2, .LBB0_9
; CHECK-NEXT: @ %bb.6: @ %while.body14.preheader
; CHECK-NEXT: lsls r6, r2, #1
-; CHECK-NEXT: mov r5, r4
-; CHECK-NEXT: mov r7, r4
+; CHECK-NEXT: mov r5, r8
+; CHECK-NEXT: mov r7, r8
; CHECK-NEXT: movs r2, #0
; CHECK-NEXT: dlstp.16 lr, r6
; CHECK-NEXT: .p2align 2
@@ -88,22 +77,22 @@ define void @arm_cmplx_dot_prod_q15(ptr noundef %pSrcA, ptr noundef %pSrcB, i32
; CHECK-NEXT: vldrh.u16 q0, [r0], #16
; CHECK-NEXT: vldrh.u16 q1, [r1], #16
; CHECK-NEXT: vmlsldava.s16 r2, r7, q0, q1
-; CHECK-NEXT: vmlaldavax.s16 r4, r5, q0, q1
+; CHECK-NEXT: vmlaldavax.s16 r8, r5, q0, q1
; CHECK-NEXT: letp lr, .LBB0_7
; CHECK-NEXT: @ %bb.8: @ %if.end.loopexit177
-; CHECK-NEXT: mov r8, r4
-; CHECK-NEXT: mov r4, r2
+; CHECK-NEXT: mov r6, r8
+; CHECK-NEXT: mov r8, r2
; CHECK-NEXT: b .LBB0_10
; CHECK-NEXT: .p2align 2
; CHECK-NEXT: .LBB0_9:
-; CHECK-NEXT: mov r7, r4
-; CHECK-NEXT: mov.w r8, #0
-; CHECK-NEXT: mov r5, r4
+; CHECK-NEXT: mov r7, r8
+; CHECK-NEXT: movs r6, #0
+; CHECK-NEXT: mov r5, r8
; CHECK-NEXT: .LBB0_10: @ %if.end
-; CHECK-NEXT: asrl r4, r7, #6
-; CHECK-NEXT: asrl r8, r5, #6
-; CHECK-NEXT: str r4, [r3]
-; CHECK-NEXT: str.w r8, [r12]
+; CHECK-NEXT: asrl r8, r7, #6
+; CHECK-NEXT: asrl r6, r5, #6
+; CHECK-NEXT: str.w r8, [r3]
+; CHECK-NEXT: str.w r6, [r12]
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, pc}
entry:
%cmp = icmp ugt i32 %numSamples, 15
>From c0884173092b828ced46058cd829b8b4aa599c54 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
Date: Thu, 19 Dec 2024 20:56:18 +0800
Subject: [PATCH 2/2] Apply review suggestions
---
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 9 ++-
llvm/test/CodeGen/Thumb2/mve-pipelineloops.ll | 75 +++++++++++--------
2 files changed, 50 insertions(+), 34 deletions(-)
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 891d0c20ebc448..ed1265846140eb 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -6936,7 +6936,6 @@ bool ARMPipelinerLoopInfo::tooMuchRegisterPressure(SwingSchedulerDAG &SSD,
RegClassInfo.runOnMachineFunction(*MF);
RPTracker.init(MF, &RegClassInfo, nullptr, EndLoop->getParent(),
EndLoop->getParent()->end(), false, false);
- const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
bumpCrossIterationPressure(RPTracker, CrossIterationNeeds);
@@ -6978,10 +6977,16 @@ bool ARMPipelinerLoopInfo::tooMuchRegisterPressure(SwingSchedulerDAG &SSD,
}
auto &P = RPTracker.getPressure().MaxSetPressure;
- for (unsigned I = 0, E = P.size(); I < E; ++I)
+ for (unsigned I = 0, E = P.size(); I < E; ++I) {
+ // Exclude some Neon register classes.
+ if (I == ARM::DQuad_with_ssub_0 || I == ARM::DTripleSpc_with_ssub_0 ||
+ I == ARM::DTriple_with_qsub_0_in_QPR)
+ continue;
+
if (P[I] > RegClassInfo.getRegPressureSetLimit(I)) {
return true;
}
+ }
return false;
}
diff --git a/llvm/test/CodeGen/Thumb2/mve-pipelineloops.ll b/llvm/test/CodeGen/Thumb2/mve-pipelineloops.ll
index 7d7a65640d3705..43ed5eefbf4c77 100644
--- a/llvm/test/CodeGen/Thumb2/mve-pipelineloops.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-pipelineloops.ll
@@ -17,40 +17,51 @@ define void @arm_cmplx_dot_prod_q15(ptr noundef %pSrcA, ptr noundef %pSrcB, i32
; CHECK-NEXT: mov.w r5, #0
; CHECK-NEXT: csel r7, r6, r5, hs
; CHECK-NEXT: add.w lr, r7, #1
-; CHECK-NEXT: mov r6, r5
-; CHECK-NEXT: vldrh.u16 q1, [r0], #32
+; CHECK-NEXT: mov r4, r5
+; CHECK-NEXT: vldrh.u16 q0, [r0], #32
; CHECK-NEXT: movs r7, #0
; CHECK-NEXT: mov r8, r5
+; CHECK-NEXT: vldrh.u16 q1, [r1], #32
+; CHECK-NEXT: vmlsldava.s16 r4, r7, q0, q1
+; CHECK-NEXT: vldrh.u16 q2, [r0, #-16]
+; CHECK-NEXT: vmlaldavax.s16 r8, r5, q0, q1
+; CHECK-NEXT: vldrh.u16 q3, [r1, #-16]
+; CHECK-NEXT: vmlsldava.s16 r4, r7, q2, q3
; CHECK-NEXT: vldrh.u16 q0, [r1], #32
+; CHECK-NEXT: sub.w lr, lr, #1
+; CHECK-NEXT: cmp.w lr, #0
+; CHECK-NEXT: vldrh.u16 q1, [r0], #32
+; CHECK-NEXT: beq .LBB0_3
; CHECK-NEXT: .p2align 2
; CHECK-NEXT: .LBB0_2: @ %while.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: vmlsldava.s16 r8, r7, q1, q0
+; CHECK-NEXT: vmlaldavax.s16 r8, r5, q2, q3
+; CHECK-NEXT: vldrh.u16 q3, [r1, #-16]
+; CHECK-NEXT: vmlsldava.s16 r4, r7, q1, q0
; CHECK-NEXT: vldrh.u16 q2, [r0, #-16]
-; CHECK-NEXT: vmlaldavax.s16 r6, r5, q1, q0
-; CHECK-NEXT: vldrh.u16 q1, [r1, #-16]
-; CHECK-NEXT: vmlsldava.s16 r8, r7, q2, q1
-; CHECK-NEXT: vldrh.u16 q0, [r1], #32
-; CHECK-NEXT: vmlaldavax.s16 r6, r5, q2, q1
+; CHECK-NEXT: vmlaldavax.s16 r8, r5, q1, q0
; CHECK-NEXT: vldrh.u16 q1, [r0], #32
+; CHECK-NEXT: vmlsldava.s16 r4, r7, q2, q3
+; CHECK-NEXT: vldrh.u16 q0, [r1], #32
; CHECK-NEXT: le lr, .LBB0_2
-; CHECK-NEXT: @ %bb.3: @ %do.body
-; CHECK-NEXT: movs r4, #14
-; CHECK-NEXT: and.w r2, r4, r2, lsl #1
-; CHECK-NEXT: vmlaldavax.s16 r6, r5, q1, q0
+; CHECK-NEXT: .LBB0_3:
+; CHECK-NEXT: vmlaldavax.s16 r8, r5, q2, q3
+; CHECK-NEXT: movs r6, #14
+; CHECK-NEXT: and.w r2, r6, r2, lsl #1
+; CHECK-NEXT: vmlaldavax.s16 r8, r5, q1, q0
; CHECK-NEXT: vldrh.u16 q2, [r0, #-16]
-; CHECK-NEXT: vmlsldava.s16 r8, r7, q1, q0
+; CHECK-NEXT: vmlsldava.s16 r4, r7, q1, q0
; CHECK-NEXT: vldrh.u16 q0, [r1, #-16]
-; CHECK-NEXT: vmlaldavax.s16 r6, r5, q2, q0
+; CHECK-NEXT: vmlaldavax.s16 r8, r5, q2, q0
; CHECK-NEXT: vctp.16 r2
-; CHECK-NEXT: vmlsldava.s16 r8, r7, q2, q0
+; CHECK-NEXT: vmlsldava.s16 r4, r7, q2, q0
; CHECK-NEXT: vpst
; CHECK-NEXT: vldrht.u16 q1, [r0]
; CHECK-NEXT: cmp r2, #9
; CHECK-NEXT: vpsttt
; CHECK-NEXT: vldrht.u16 q0, [r1]
-; CHECK-NEXT: vmlsldavat.s16 r8, r7, q1, q0
-; CHECK-NEXT: vmlaldavaxt.s16 r6, r5, q1, q0
+; CHECK-NEXT: vmlsldavat.s16 r4, r7, q1, q0
+; CHECK-NEXT: vmlaldavaxt.s16 r8, r5, q1, q0
; CHECK-NEXT: blo .LBB0_10
; CHECK-NEXT: @ %bb.4: @ %do.body.1
; CHECK-NEXT: subs r2, #8
@@ -58,17 +69,17 @@ define void @arm_cmplx_dot_prod_q15(ptr noundef %pSrcA, ptr noundef %pSrcB, i32
; CHECK-NEXT: vpstttt
; CHECK-NEXT: vldrht.u16 q0, [r0, #16]
; CHECK-NEXT: vldrht.u16 q1, [r1, #16]
-; CHECK-NEXT: vmlsldavat.s16 r8, r7, q0, q1
-; CHECK-NEXT: vmlaldavaxt.s16 r6, r5, q0, q1
+; CHECK-NEXT: vmlsldavat.s16 r4, r7, q0, q1
+; CHECK-NEXT: vmlaldavaxt.s16 r8, r5, q0, q1
; CHECK-NEXT: b .LBB0_10
; CHECK-NEXT: .p2align 2
; CHECK-NEXT: .LBB0_5: @ %if.else
-; CHECK-NEXT: mov.w r8, #0
+; CHECK-NEXT: mov.w r4, #0
; CHECK-NEXT: cbz r2, .LBB0_9
; CHECK-NEXT: @ %bb.6: @ %while.body14.preheader
; CHECK-NEXT: lsls r6, r2, #1
-; CHECK-NEXT: mov r5, r8
-; CHECK-NEXT: mov r7, r8
+; CHECK-NEXT: mov r5, r4
+; CHECK-NEXT: mov r7, r4
; CHECK-NEXT: movs r2, #0
; CHECK-NEXT: dlstp.16 lr, r6
; CHECK-NEXT: .p2align 2
@@ -77,22 +88,22 @@ define void @arm_cmplx_dot_prod_q15(ptr noundef %pSrcA, ptr noundef %pSrcB, i32
; CHECK-NEXT: vldrh.u16 q0, [r0], #16
; CHECK-NEXT: vldrh.u16 q1, [r1], #16
; CHECK-NEXT: vmlsldava.s16 r2, r7, q0, q1
-; CHECK-NEXT: vmlaldavax.s16 r8, r5, q0, q1
+; CHECK-NEXT: vmlaldavax.s16 r4, r5, q0, q1
; CHECK-NEXT: letp lr, .LBB0_7
; CHECK-NEXT: @ %bb.8: @ %if.end.loopexit177
-; CHECK-NEXT: mov r6, r8
-; CHECK-NEXT: mov r8, r2
+; CHECK-NEXT: mov r8, r4
+; CHECK-NEXT: mov r4, r2
; CHECK-NEXT: b .LBB0_10
; CHECK-NEXT: .p2align 2
; CHECK-NEXT: .LBB0_9:
-; CHECK-NEXT: mov r7, r8
-; CHECK-NEXT: movs r6, #0
-; CHECK-NEXT: mov r5, r8
+; CHECK-NEXT: mov r7, r4
+; CHECK-NEXT: mov.w r8, #0
+; CHECK-NEXT: mov r5, r4
; CHECK-NEXT: .LBB0_10: @ %if.end
-; CHECK-NEXT: asrl r8, r7, #6
-; CHECK-NEXT: asrl r6, r5, #6
-; CHECK-NEXT: str.w r8, [r3]
-; CHECK-NEXT: str.w r6, [r12]
+; CHECK-NEXT: asrl r4, r7, #6
+; CHECK-NEXT: asrl r8, r5, #6
+; CHECK-NEXT: str r4, [r3]
+; CHECK-NEXT: str.w r8, [r12]
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, pc}
entry:
%cmp = icmp ugt i32 %numSamples, 15
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