[llvm] Reland "[RISCV] Add scheduling model for mips p8700 CPU" (PR #120550)

[Pengcheng Wang via llvm-commits]

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+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=mips-p8700 -timeline -iterations=1 < %s | FileCheck %s
+
+# A few instructions to test the pipeline:
+# - Integer division (IDiv) exercises the p8700GpDiv resource.
+# - Integer multiplication (IMul) uses p8700GpMul.
+# - Floating-point multiplication uses the FPUL pipeline.
+# - Load/Store instructions use the LSU pipeline.
+# - Simple ALU instructions test the p8700WriteEitherALU and p8700IssueAL2 resources.
+# - A jump instruction to test the CTI pipeline.
+
+  .text
+  .globl _start
+_start:
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wangpc-pp wrote:

Actually you don't need this in a MCA test. :-)

https://github.com/llvm/llvm-project/pull/120550