[llvm] [RISCV] Add scheduling model for mips p8700 CPU (PR #119885)

[LLVM Continuous Integration via llvm-commits]

llvm-ci wrote:

LLVM Buildbot has detected a new failure on builder `premerge-monolithic-linux` running on `premerge-linux-1` while building `llvm` at step 6 "build-unified-tree".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/153/builds/18043

<details>
<summary>Here is the relevant piece of the build log for the reference</summary>

```
Step 6 (build-unified-tree) failure: build (failure)
...
1.905 [3405/16/20] Linking CXX executable bin/llvm-config
1.988 [3405/15/21] Building RISCVGenO0PreLegalizeGICombiner.inc...
2.020 [3405/14/22] Building RISCVGenDisassemblerTables.inc...
2.033 [3405/13/23] Building RISCVGenPreLegalizeGICombiner.inc...
2.049 [3405/12/24] Building RISCVGenPostLegalizeGICombiner.inc...
2.067 [3405/11/25] Building RISCVGenMCCodeEmitter.inc...
2.118 [3405/10/26] Building RISCVGenAsmWriter.inc...
2.159 [3405/9/27] Building RISCVGenAsmMatcher.inc...
2.619 [3405/8/28] Building RISCVGenSearchableTables.inc...
3.188 [3405/7/29] Building RISCVGenSubtargetInfo.inc...
FAILED: lib/Target/RISCV/RISCVGenSubtargetInfo.inc /build/buildbot/premerge-monolithic-linux/build/lib/Target/RISCV/RISCVGenSubtargetInfo.inc 
cd /build/buildbot/premerge-monolithic-linux/build && /build/buildbot/premerge-monolithic-linux/build/bin/llvm-tblgen -gen-subtarget -I /build/buildbot/premerge-monolithic-linux/llvm-project/llvm/lib/Target/RISCV -I/build/buildbot/premerge-monolithic-linux/build/include -I/build/buildbot/premerge-monolithic-linux/llvm-project/llvm/include -I /build/buildbot/premerge-monolithic-linux/llvm-project/llvm/lib/Target /build/buildbot/premerge-monolithic-linux/llvm-project/llvm/lib/Target/RISCV/RISCV.td --write-if-changed -o lib/Target/RISCV/RISCVGenSubtargetInfo.inc -d lib/Target/RISCV/RISCVGenSubtargetInfo.inc.d
Included from /build/buildbot/premerge-monolithic-linux/llvm-project/llvm/lib/Target/RISCV/RISCV.td:49:
/build/buildbot/premerge-monolithic-linux/llvm-project/llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td:20:5: error: Processor does not define resources for WriteFCvtF32ToF16
def MIPSP8700Model : SchedMachineModel {
    ^
4.589 [3405/6/30] Building CXX object lib/Object/CMakeFiles/LLVMObject.dir/IRSymtab.cpp.o
7.563 [3405/5/31] Building RISCVGenInstrInfo.inc...
9.425 [3405/4/32] Building RISCVGenGlobalISel.inc...
10.623 [3405/3/33] Building RISCVGenDAGISel.inc...
13.095 [3405/2/34] Building CXX object lib/CodeGen/AsmPrinter/CMakeFiles/LLVMAsmPrinter.dir/AsmPrinter.cpp.o
14.380 [3405/1/35] Building CXX object lib/LTO/CMakeFiles/LLVMLTO.dir/LTO.cpp.o
ninja: build stopped: subcommand failed.

```

</details>

https://github.com/llvm/llvm-project/pull/119885