[llvm] [RISCV] Add scheduling model for mips p8700 CPU (PR #119885)

[LLVM Continuous Integration via llvm-commits]

llvm-ci wrote:

LLVM Buildbot has detected a new failure on builder `ml-opt-rel-x86-64` running on `ml-opt-rel-x86-64-b2` while building `llvm` at step 5 "build-unified-tree".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/185/builds/10485

<details>
<summary>Here is the relevant piece of the build log for the reference</summary>

```
Step 5 (build-unified-tree) failure: build (failure)
...
27.373 [2282/64/1406] Linking CXX static library lib/libLLVMBitReader.a
27.377 [2281/64/1407] Linking CXX static library lib/libLLVMBPFInfo.a
27.399 [2280/64/1408] Linking CXX static library lib/libLLVMCFGuard.a
27.417 [2279/64/1409] Linking CXX static library lib/libLLVMHexagonInfo.a
27.429 [2278/64/1410] Linking CXX static library lib/libLLVMLanaiInfo.a
27.433 [2277/64/1411] Linking CXX static library lib/libLLVMAVRDisassembler.a
27.455 [2276/64/1412] Linking CXX static library lib/libLLVMLoongArchInfo.a
27.484 [2275/64/1413] Linking CXX static library lib/libLLVMAVRDesc.a
27.487 [2274/64/1414] Linking CXX static library lib/libLLVMBPFDisassembler.a
27.503 [2273/64/1415] Building RISCVGenSubtargetInfo.inc...
FAILED: lib/Target/RISCV/RISCVGenSubtargetInfo.inc /b/ml-opt-rel-x86-64-b1/build/lib/Target/RISCV/RISCVGenSubtargetInfo.inc 
cd /b/ml-opt-rel-x86-64-b1/build && /b/ml-opt-rel-x86-64-b1/build/bin/llvm-tblgen -gen-subtarget -I /b/ml-opt-rel-x86-64-b1/llvm-project/llvm/lib/Target/RISCV -I/var/lib/buildbot/.local/lib/python3.7/site-packages/tensorflow/include -I/b/ml-opt-rel-x86-64-b1/build/include -I/b/ml-opt-rel-x86-64-b1/llvm-project/llvm/include -I /b/ml-opt-rel-x86-64-b1/llvm-project/llvm/lib/Target /b/ml-opt-rel-x86-64-b1/llvm-project/llvm/lib/Target/RISCV/RISCV.td --write-if-changed -o lib/Target/RISCV/RISCVGenSubtargetInfo.inc -d lib/Target/RISCV/RISCVGenSubtargetInfo.inc.d
Included from /b/ml-opt-rel-x86-64-b1/llvm-project/llvm/lib/Target/RISCV/RISCV.td:49:
/b/ml-opt-rel-x86-64-b1/llvm-project/llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td:20:5: error: Processor does not define resources for WriteFCvtF32ToF16
def MIPSP8700Model : SchedMachineModel {
    ^
27.519 [2273/63/1416] Linking CXX static library lib/libLLVMLanaiDesc.a
27.535 [2273/62/1417] Linking CXX static library lib/libLLVMBPFDesc.a
27.541 [2273/61/1418] Linking CXX static library lib/libLLVMMipsInfo.a
27.544 [2273/60/1419] Linking CXX static library lib/libLLVMHexagonDesc.a
27.557 [2273/59/1420] Linking CXX static library lib/libLLVMLoongArchDesc.a
27.589 [2273/58/1421] Linking CXX static library lib/libLLVMMSP430Info.a
27.601 [2273/57/1422] Linking CXX static library lib/libLLVMNVPTXInfo.a
27.641 [2273/56/1423] Building WebAssemblyGenAsmWriter.inc...
27.684 [2273/55/1424] Building XCoreGenCallingConv.inc...
27.716 [2273/54/1425] Building XCoreGenSubtargetInfo.inc...
27.748 [2273/53/1426] Building WebAssemblyGenDisassemblerTables.inc...
27.851 [2273/52/1427] Building XCoreGenDisassemblerTables.inc...
27.859 [2273/51/1428] Building CXX object lib/Object/CMakeFiles/LLVMObject.dir/IRSymtab.cpp.o
27.929 [2273/50/1429] Building XCoreGenInstrInfo.inc...
27.953 [2273/49/1430] Building WebAssemblyGenMCCodeEmitter.inc...
28.001 [2273/48/1431] Building WebAssemblyGenRegisterInfo.inc...
28.017 [2273/47/1432] Building WebAssemblyGenSubtargetInfo.inc...
28.024 [2273/46/1433] Building XCoreGenRegisterInfo.inc...
28.056 [2273/45/1434] Building XCoreGenAsmWriter.inc...
28.058 [2273/44/1435] Building WebAssemblyGenAsmMatcher.inc...
28.102 [2273/43/1436] Building WebAssemblyGenInstrInfo.inc...
28.360 [2273/42/1437] Building XCoreGenDAGISel.inc...
28.600 [2273/41/1438] Building WebAssemblyGenDAGISel.inc...
28.622 [2273/40/1439] Building WebAssemblyGenFastISel.inc...
28.805 [2273/39/1440] Building VEGenRegisterInfo.inc...
29.280 [2273/38/1441] Building VEGenMCCodeEmitter.inc...
29.422 [2273/37/1442] Building VEGenSubtargetInfo.inc...
31.985 [2273/36/1443] Building X86GenCallingConv.inc...
32.139 [2273/35/1444] Building X86GenExegesis.inc...
32.548 [2273/34/1445] Building X86GenRegisterBank.inc...
32.750 [2273/33/1446] Building X86GenRegisterInfo.inc...
33.545 [2273/32/1447] Building X86GenAsmWriter.inc...
33.786 [2273/31/1448] Building X86GenDisassemblerTables.inc...

```

</details>

https://github.com/llvm/llvm-project/pull/119885