[llvm] ARM: Handle vldrh and vstrh in stack access hooks (PR #120527)

[Matt Arsenault via llvm-commits]

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/120527

This is to help avoid regressions in a future regalloc patch.

I do not see the vstrh case appear in tests. There also appear
to be other cases unhandled here, like LDRBi12.

>From 5c434fe208a90998f6168fc8ba22aec26b760d60 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Thu, 19 Dec 2024 13:16:28 +0700
Subject: [PATCH] ARM: Handle vldrh and vstrh in stack access hooks

This is to help avoid regressions in a future regalloc patch.

I do not see the vstrh case appear in tests. There also appear
to be other cases unhandled here, like LDRBi12.
---
 llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index e6b37dd9161685..e3e2e83fd5c7eb 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -1330,6 +1330,7 @@ Register ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
   case ARM::tSTRspi:
   case ARM::VSTRD:
   case ARM::VSTRS:
+  case ARM::VSTRH:
   case ARM::VSTR_P0_off:
   case ARM::VSTR_FPSCR_NZCVQC_off:
   case ARM::MVE_VSTRWU32:
@@ -1588,6 +1589,7 @@ Register ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
   case ARM::tLDRspi:
   case ARM::VLDRD:
   case ARM::VLDRS:
+  case ARM::VLDRH:
   case ARM::VLDR_P0_off:
   case ARM::VLDR_FPSCR_NZCVQC_off:
   case ARM::MVE_VLDRWU32: