[llvm] RISCV: Implement isLoadFromStackSlot/isStoreToStackSlot for rvv (PR #120524)

[Matt Arsenault via llvm-commits]

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@@ -118,6 +118,12 @@ Register RISCVInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
   case RISCV::FLD:
     MemBytes = 8;
     break;
+  case RISCV::VL8RE8_V:
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arsenm wrote:

I never see the spill pseudos appear here for some reason 

https://github.com/llvm/llvm-project/pull/120524