[llvm] [RISCV] Addi optimization ported to GISel (PR #120463)

[Craig Topper via llvm-commits]

topperc wrote:

> @benshi001 or @topperc I had one question about the add64_accept test. I don't really understand what the point of the sltu instruction in that cases is but both GISel and ISel have that instruction. It seems like it shouldn't be there in either or am I missing a overflow check semantic or something?

That test does 64-bit arithmetic. On RV32, the registers are only 32 bits wide so we have to split the addition. The sltu is determining if there was a carry out of the low half because RISC-V doesn't have flags. So we have to manually detect overflow by checking if the result of the low half add is smaller than one of the inputs.

https://github.com/llvm/llvm-project/pull/120463