[llvm] c3241a9 - [AMDGPU][True16][MC] test update for v_subrev_f16 in true16 (#119315)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 18 10:01:12 PST 2024
Author: Brox Chen
Date: 2024-12-18T13:01:08-05:00
New Revision: c3241a9a4de3ef71a82f9434f84fa7437fe43f9a
URL: https://github.com/llvm/llvm-project/commit/c3241a9a4de3ef71a82f9434f84fa7437fe43f9a
DIFF: https://github.com/llvm/llvm-project/commit/c3241a9a4de3ef71a82f9434f84fa7437fe43f9a.diff
LOG: [AMDGPU][True16][MC] test update for v_subrev_f16 in true16 (#119315)
This is a NFC change. Update mc test for v_subrev_f16 in true16 format.
MC source change was done by previous patch and automatically enabled by
t16 pesudo
Added:
Modified:
llvm/lib/Target/AMDGPU/VOP2Instructions.td
llvm/test/MC/AMDGPU/gfx11_asm_vop2.s
llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp16.s
llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp8.s
llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_err.s
llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_promote.s
llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vop2.s
llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vop2.s
llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vop2.s
llvm/test/MC/AMDGPU/gfx12_asm_vop2.s
llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp16.s
llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp8.s
llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_err.s
llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_promote.s
llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2.s
llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2_dpp16.s
llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2_dpp8.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/VOP2Instructions.td b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
index cafce9ffce41a6..ca4a0fa706c301 100644
--- a/llvm/lib/Target/AMDGPU/VOP2Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
@@ -1820,8 +1820,7 @@ defm V_PK_FMAC_F16 : VOP2_Real_e32_gfx11_gfx12<0x03c>;
defm V_ADD_F16 : VOP2_Real_FULL_t16_and_fake16_gfx11_gfx12<0x032, "v_add_f16">;
defm V_SUB_F16 : VOP2_Real_FULL_t16_and_fake16_gfx11_gfx12<0x033, "v_sub_f16">;
-defm V_SUBREV_F16_t16 : VOP2_Real_FULL_t16_gfx11_gfx12<0x034, "v_subrev_f16">;
-defm V_SUBREV_F16_fake16 : VOP2_Real_FULL_t16_gfx11_gfx12<0x034, "v_subrev_f16">;
+defm V_SUBREV_F16 : VOP2_Real_FULL_t16_and_fake16_gfx11_gfx12<0x034, "v_subrev_f16">;
defm V_MUL_F16 : VOP2_Real_FULL_t16_and_fake16_gfx11_gfx12<0x035, "v_mul_f16">;
defm V_FMAC_F16 : VOP2_Real_FULL_t16_and_fake16_gfx11_gfx12<0x036, "v_fmac_f16">;
defm V_LDEXP_F16 : VOP2_Real_FULL_t16_and_fake16_gfx11_gfx12<0x03b, "v_ldexp_f16">;
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop2.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop2.s
index 0aafb64b4ce2e5..163010adf7bd4b 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop2.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop2.s
@@ -2437,50 +2437,65 @@ v_subrev_co_ci_u32 v255, vcc, 0xaf123456, v255, vcc
// W64: v_subrev_co_ci_u32_e32 v255, vcc, 0xaf123456, v255, vcc ; encoding: [0xff,0xfe,0xff,0x45,0x56,0x34,0x12,0xaf]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_subrev_f16 v5, v1, v2
-// GFX11: v_subrev_f16_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x68]
+v_subrev_f16 v5.l, v1.l, v2.l
+// GFX11: v_subrev_f16_e32 v5.l, v1.l, v2.l ; encoding: [0x01,0x05,0x0a,0x68]
-v_subrev_f16 v5, v127, v2
-// GFX11: v_subrev_f16_e32 v5, v127, v2 ; encoding: [0x7f,0x05,0x0a,0x68]
+v_subrev_f16 v5.l, v127.l, v2.l
+// GFX11: v_subrev_f16_e32 v5.l, v127.l, v2.l ; encoding: [0x7f,0x05,0x0a,0x68]
-v_subrev_f16 v5, s1, v2
-// GFX11: v_subrev_f16_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x68]
+v_subrev_f16 v5.l, s1, v2.l
+// GFX11: v_subrev_f16_e32 v5.l, s1, v2.l ; encoding: [0x01,0x04,0x0a,0x68]
-v_subrev_f16 v5, s105, v2
-// GFX11: v_subrev_f16_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x68]
+v_subrev_f16 v5.l, s105, v2.l
+// GFX11: v_subrev_f16_e32 v5.l, s105, v2.l ; encoding: [0x69,0x04,0x0a,0x68]
-v_subrev_f16 v5, vcc_lo, v2
-// GFX11: v_subrev_f16_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x68]
+v_subrev_f16 v5.l, vcc_lo, v2.l
+// GFX11: v_subrev_f16_e32 v5.l, vcc_lo, v2.l ; encoding: [0x6a,0x04,0x0a,0x68]
-v_subrev_f16 v5, vcc_hi, v2
-// GFX11: v_subrev_f16_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x68]
+v_subrev_f16 v5.l, vcc_hi, v2.l
+// GFX11: v_subrev_f16_e32 v5.l, vcc_hi, v2.l ; encoding: [0x6b,0x04,0x0a,0x68]
-v_subrev_f16 v5, ttmp15, v2
-// GFX11: v_subrev_f16_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x68]
+v_subrev_f16 v5.l, ttmp15, v2.l
+// GFX11: v_subrev_f16_e32 v5.l, ttmp15, v2.l ; encoding: [0x7b,0x04,0x0a,0x68]
-v_subrev_f16 v5, m0, v2
-// GFX11: v_subrev_f16_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x68]
+v_subrev_f16 v5.l, m0, v2.l
+// GFX11: v_subrev_f16_e32 v5.l, m0, v2.l ; encoding: [0x7d,0x04,0x0a,0x68]
-v_subrev_f16 v5, exec_lo, v2
-// GFX11: v_subrev_f16_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x68]
+v_subrev_f16 v5.l, exec_lo, v2.l
+// GFX11: v_subrev_f16_e32 v5.l, exec_lo, v2.l ; encoding: [0x7e,0x04,0x0a,0x68]
-v_subrev_f16 v5, exec_hi, v2
-// GFX11: v_subrev_f16_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x68]
+v_subrev_f16 v5.l, exec_hi, v2.l
+// GFX11: v_subrev_f16_e32 v5.l, exec_hi, v2.l ; encoding: [0x7f,0x04,0x0a,0x68]
-v_subrev_f16 v5, null, v2
-// GFX11: v_subrev_f16_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x68]
+v_subrev_f16 v5.l, null, v2.l
+// GFX11: v_subrev_f16_e32 v5.l, null, v2.l ; encoding: [0x7c,0x04,0x0a,0x68]
-v_subrev_f16 v5, -1, v2
-// GFX11: v_subrev_f16_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x68]
+v_subrev_f16 v5.l, -1, v2.l
+// GFX11: v_subrev_f16_e32 v5.l, -1, v2.l ; encoding: [0xc1,0x04,0x0a,0x68]
-v_subrev_f16 v5, 0.5, v2
-// GFX11: v_subrev_f16_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x68]
+v_subrev_f16 v5.l, 0.5, v2.l
+// GFX11: v_subrev_f16_e32 v5.l, 0.5, v2.l ; encoding: [0xf0,0x04,0x0a,0x68]
-v_subrev_f16 v5, src_scc, v2
-// GFX11: v_subrev_f16_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x68]
+v_subrev_f16 v5.l, src_scc, v2.l
+// GFX11: v_subrev_f16_e32 v5.l, src_scc, v2.l ; encoding: [0xfd,0x04,0x0a,0x68]
-v_subrev_f16 v127, 0xfe0b, v127
-// GFX11: v_subrev_f16_e32 v127, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfe,0x68,0x0b,0xfe,0x00,0x00]
+v_subrev_f16 v127.l, 0xfe0b, v127.l
+// GFX11: v_subrev_f16_e32 v127.l, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0xfe,0x68,0x0b,0xfe,0x00,0x00]
+
+v_subrev_f16 v5.l, v1.h, v2.l
+// GFX11: v_subrev_f16_e32 v5.l, v1.h, v2.l ; encoding: [0x81,0x05,0x0a,0x68]
+
+v_subrev_f16 v5.l, v127.h, v2.l
+// GFX11: v_subrev_f16_e32 v5.l, v127.h, v2.l ; encoding: [0xff,0x05,0x0a,0x68]
+
+v_subrev_f16 v127.l, 0.5, v127.l
+// GFX11: v_subrev_f16_e32 v127.l, 0.5, v127.l ; encoding: [0xf0,0xfe,0xfe,0x68]
+
+v_subrev_f16 v5.h, src_scc, v2.h
+// GFX11: v_subrev_f16_e32 v5.h, src_scc, v2.h ; encoding: [0xfd,0x04,0x0b,0x69]
+
+v_subrev_f16 v127.h, 0xfe0b, v127.h
+// GFX11: v_subrev_f16_e32 v127.h, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0xff,0x69,0x0b,0xfe,0x00,0x00]
v_subrev_f32 v5, v1, v2
// GFX11: v_subrev_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x0a]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp16.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp16.s
index f05d94cdb6c144..2695059853b086 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp16.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp16.s
@@ -1958,47 +1958,56 @@ v_subrev_co_ci_u32 v255, vcc, v255, v255, vcc row_xmask:15 row_mask:0x3 bank_mas
// W64: v_subrev_co_ci_u32_dpp v255, vcc, v255, v255, vcc row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x45,0xff,0x6f,0x05,0x30]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_subrev_f16 v5, v1, v2 quad_perm:[3,2,1,0]
-// GFX11: v_subrev_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x1b,0x00,0xff]
+v_subrev_f16 v5.l, v1.l, v2.l quad_perm:[3,2,1,0]
+// GFX11: v_subrev_f16_dpp v5.l, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x1b,0x00,0xff]
-v_subrev_f16 v5, v1, v2 quad_perm:[0,1,2,3]
-// GFX11: v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0xff]
+v_subrev_f16 v5.l, v1.l, v2.l quad_perm:[0,1,2,3]
+// GFX11: v_subrev_f16_dpp v5.l, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0xff]
-v_subrev_f16 v5, v1, v2 row_mirror
-// GFX11: v_subrev_f16_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x40,0x01,0xff]
+v_subrev_f16 v5.l, v1.l, v2.l row_mirror
+// GFX11: v_subrev_f16_dpp v5.l, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x40,0x01,0xff]
-v_subrev_f16 v5, v1, v2 row_half_mirror
-// GFX11: v_subrev_f16_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x41,0x01,0xff]
+v_subrev_f16 v5.l, v1.l, v2.l row_half_mirror
+// GFX11: v_subrev_f16_dpp v5.l, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x41,0x01,0xff]
-v_subrev_f16 v5, v1, v2 row_shl:1
-// GFX11: v_subrev_f16_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x01,0x01,0xff]
+v_subrev_f16 v5.l, v1.l, v2.l row_shl:1
+// GFX11: v_subrev_f16_dpp v5.l, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x01,0x01,0xff]
-v_subrev_f16 v5, v1, v2 row_shl:15
-// GFX11: v_subrev_f16_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x0f,0x01,0xff]
+v_subrev_f16 v5.l, v1.l, v2.l row_shl:15
+// GFX11: v_subrev_f16_dpp v5.l, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x0f,0x01,0xff]
-v_subrev_f16 v5, v1, v2 row_shr:1
-// GFX11: v_subrev_f16_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x11,0x01,0xff]
+v_subrev_f16 v5.l, v1.l, v2.l row_shr:1
+// GFX11: v_subrev_f16_dpp v5.l, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x11,0x01,0xff]
-v_subrev_f16 v5, v1, v2 row_shr:15
-// GFX11: v_subrev_f16_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x1f,0x01,0xff]
+v_subrev_f16 v5.l, v1.l, v2.l row_shr:15
+// GFX11: v_subrev_f16_dpp v5.l, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x1f,0x01,0xff]
-v_subrev_f16 v5, v1, v2 row_ror:1
-// GFX11: v_subrev_f16_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x21,0x01,0xff]
+v_subrev_f16 v5.l, v1.l, v2.l row_ror:1
+// GFX11: v_subrev_f16_dpp v5.l, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x21,0x01,0xff]
-v_subrev_f16 v5, v1, v2 row_ror:15
-// GFX11: v_subrev_f16_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x2f,0x01,0xff]
+v_subrev_f16 v5.l, v1.l, v2.l row_ror:15
+// GFX11: v_subrev_f16_dpp v5.l, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x2f,0x01,0xff]
-v_subrev_f16 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
-// GFX11: v_subrev_f16_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x50,0x01,0xff]
+v_subrev_f16 v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf
+// GFX11: v_subrev_f16_dpp v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x50,0x01,0xff]
-v_subrev_f16 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
-// GFX11: v_subrev_f16_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x5f,0x01,0x01]
+v_subrev_f16 v5.l, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX11: v_subrev_f16_dpp v5.l, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x5f,0x01,0x01]
-v_subrev_f16 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
-// GFX11: v_subrev_f16_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x60,0x09,0x13]
+v_subrev_f16 v5.l, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1
+// GFX11: v_subrev_f16_dpp v5.l, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x60,0x09,0x13]
-v_subrev_f16 v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
-// GFX11: v_subrev_f16_dpp v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x68,0x7f,0x6f,0xf5,0x30]
+v_subrev_f16 v127.l, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1
+// GFX11: v_subrev_f16_dpp v127.l, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x68,0x7f,0x6f,0xf5,0x30]
+
+v_subrev_f16 v127.l, v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX11: v_subrev_f16_dpp v127.l, v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xfe,0xfe,0x68,0x7f,0x5f,0x01,0x01]
+
+v_subrev_f16 v5.h, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX11: v_subrev_f16_dpp v5.h, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0b,0x69,0x81,0x60,0x09,0x13]
+
+v_subrev_f16 v127.h, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX11: v_subrev_f16_dpp v127.h, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x69,0xff,0x6f,0xf5,0x30]
v_subrev_f32 v5, v1, v2 quad_perm:[3,2,1,0]
// GFX11: v_subrev_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x1b,0x00,0xff]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp8.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp8.s
index f6501a72ebdd8b..b379a5d06b99b6 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp8.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp8.s
@@ -463,14 +463,23 @@ v_subrev_co_ci_u32 v255, vcc, v255, v255, vcc dpp8:[0,0,0,0,0,0,0,0] fi:0
// W64: v_subrev_co_ci_u32_dpp v255, vcc, v255, v255, vcc dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0xff,0x45,0xff,0x00,0x00,0x00]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_subrev_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
-// GFX11: v_subrev_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x68,0x01,0x77,0x39,0x05]
+v_subrev_f16 v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: v_subrev_f16_dpp v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x68,0x01,0x77,0x39,0x05]
-v_subrev_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
-// GFX11: v_subrev_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x0a,0x68,0x01,0x77,0x39,0x05]
+v_subrev_f16 v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX11: v_subrev_f16_dpp v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x0a,0x68,0x01,0x77,0x39,0x05]
-v_subrev_f16 v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
-// GFX11: v_subrev_f16_dpp v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0xfe,0x68,0x7f,0x00,0x00,0x00]
+v_subrev_f16 v127.l, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0]
+// GFX11: v_subrev_f16_dpp v127.l, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0xfe,0x68,0x7f,0x00,0x00,0x00]
+
+v_subrev_f16 v127.l, v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: v_subrev_f16_dpp v127.l, v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xfe,0xfe,0x68,0x7f,0x77,0x39,0x05]
+
+v_subrev_f16 v5.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX11: v_subrev_f16_dpp v5.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x0b,0x69,0x81,0x77,0x39,0x05]
+
+v_subrev_f16 v127.h, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX11: v_subrev_f16_dpp v127.h, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0xff,0x69,0xff,0x00,0x00,0x00]
v_subrev_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
// GFX11: v_subrev_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x0a,0x01,0x77,0x39,0x05]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_err.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_err.s
index 54b17209f8343a..a3abd22a143e6a 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_err.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_err.s
@@ -416,30 +416,56 @@ v_sub_f16_e32 v5.l, v1.l, v255.l
v_sub_f16_e32 v5.l, v255.l, v2.l
// GFX11: :[[@LINE-1]]:21: error: invalid operand for instruction
-v_subrev_f16_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
-// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_subrev_f16_dpp v255.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: :[[@LINE-1]]:18: error: invalid operand for instruction
-v_subrev_f16_dpp v255, v1, v2 quad_perm:[3,2,1,0]
-// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_subrev_f16_dpp v255.h, v1.h, v2.h quad_perm:[3,2,1,0]
+// GFX11: :[[@LINE-1]]:18: error: invalid operand for instruction
-v_subrev_f16_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
-// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_subrev_f16_dpp v255.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: :[[@LINE-1]]:18: error: invalid operand for instruction
+v_subrev_f16_dpp v255.l, v1.l, v2.l quad_perm:[3,2,1,0]
+// GFX11: :[[@LINE-1]]:18: error: invalid operand for instruction
-v_subrev_f16_dpp v5, v1, v255 quad_perm:[3,2,1,0]
-// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_subrev_f16_dpp v5.h, v1.h, v255.h dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: :[[@LINE-1]]:30: error: invalid operand for instruction
-v_subrev_f16_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0]
-// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_subrev_f16_dpp v5.h, v1.h, v255.h quad_perm:[3,2,1,0]
+// GFX11: :[[@LINE-1]]:30: error: invalid operand for instruction
-v_subrev_f16_dpp v5, v255, v2 quad_perm:[3,2,1,0]
-// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_subrev_f16_dpp v5.h, v255.h, v2.h dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: :[[@LINE-1]]:24: error: invalid operand for instruction
-v_subrev_f16_e32 v255, v1, v2
-// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_subrev_f16_dpp v5.h, v255.h, v2.h quad_perm:[3,2,1,0]
+// GFX11: :[[@LINE-1]]:24: error: invalid operand for instruction
-v_subrev_f16_e32 v5, v1, v255
-// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_subrev_f16_dpp v5.l, v1.l, v255.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: :[[@LINE-1]]:30: error: invalid operand for instruction
-v_subrev_f16_e32 v5, v255, v2
-// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_subrev_f16_dpp v5.l, v1.l, v255.l quad_perm:[3,2,1,0]
+// GFX11: :[[@LINE-1]]:30: error: invalid operand for instruction
+
+v_subrev_f16_dpp v5.l, v255.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: :[[@LINE-1]]:24: error: invalid operand for instruction
+
+v_subrev_f16_dpp v5.l, v255.l, v2.l quad_perm:[3,2,1,0]
+// GFX11: :[[@LINE-1]]:24: error: invalid operand for instruction
+
+v_subrev_f16_e32 v255.h, v1.h, v2.h
+// GFX11: :[[@LINE-1]]:18: error: invalid operand for instruction
+
+v_subrev_f16_e32 v255.l, v1.l, v2.l
+// GFX11: :[[@LINE-1]]:18: error: invalid operand for instruction
+
+v_subrev_f16_e32 v5.h, v1.h, v255.h
+// GFX11: :[[@LINE-1]]:30: error: invalid operand for instruction
+
+v_subrev_f16_e32 v5.h, v255.h, v2.h
+// GFX11: :[[@LINE-1]]:24: error: invalid operand for instruction
+
+v_subrev_f16_e32 v5.l, v1.l, v255.l
+// GFX11: :[[@LINE-1]]:30: error: invalid operand for instruction
+
+v_subrev_f16_e32 v5.l, v255.l, v2.l
+// GFX11: :[[@LINE-1]]:24: error: invalid operand for instruction
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_promote.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_promote.s
index 2582565f3a1082..b289a4c9aa6502 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_promote.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_promote.s
@@ -335,30 +335,56 @@ v_sub_f16 v5.l, v255.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
v_sub_f16 v5.l, v255.l, v2.l quad_perm:[3,2,1,0]
// GFX11: v_sub_f16_e64_dpp v5.l, v255.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x33,0xd5,0xfa,0x04,0x02,0x00,0xff,0x1b,0x00,0xff]
-v_subrev_f16 v255, v1, v2
-// GFX11: v_subrev_f16_e64 v255, v1, v2 ; encoding: [0xff,0x00,0x34,0xd5,0x01,0x05,0x02,0x00]
+v_subrev_f16 v255.h, v1.h, v2.h
+// GFX11: v_subrev_f16_e64 v255.h, v1.h, v2.h op_sel:[1,1,1] ; encoding: [0xff,0x58,0x34,0xd5,0x01,0x05,0x02,0x00]
-v_subrev_f16 v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
-// GFX11: v_subrev_f16_e64_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xff,0x00,0x34,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+v_subrev_f16 v255.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: v_subrev_f16_e64_dpp v255.h, v1.h, v2.h op_sel:[1,1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xff,0x58,0x34,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
-v_subrev_f16 v255, v1, v2 quad_perm:[3,2,1,0]
-// GFX11: v_subrev_f16_e64_dpp v255, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xff,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+v_subrev_f16 v255.h, v1.h, v2.h quad_perm:[3,2,1,0]
+// GFX11: v_subrev_f16_e64_dpp v255.h, v1.h, v2.h op_sel:[1,1,1] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xff,0x58,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
-v_subrev_f16 v5, v1, v255
-// GFX11: v_subrev_f16_e64 v5, v1, v255 ; encoding: [0x05,0x00,0x34,0xd5,0x01,0xff,0x03,0x00]
+v_subrev_f16 v255.l, v1.l, v2.l
+// GFX11: v_subrev_f16_e64 v255.l, v1.l, v2.l ; encoding: [0xff,0x00,0x34,0xd5,0x01,0x05,0x02,0x00]
-v_subrev_f16 v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
-// GFX11: v_subrev_f16_e64_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x34,0xd5,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05]
+v_subrev_f16 v255.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: v_subrev_f16_e64_dpp v255.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xff,0x00,0x34,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+v_subrev_f16 v255.l, v1.l, v2.l quad_perm:[3,2,1,0]
+// GFX11: v_subrev_f16_e64_dpp v255.l, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xff,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
-v_subrev_f16 v5, v1, v255 quad_perm:[3,2,1,0]
-// GFX11: v_subrev_f16_e64_dpp v5, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff]
+v_subrev_f16 v5.h, v1.h, v255.h
+// GFX11: v_subrev_f16_e64 v5.h, v1.h, v255.h op_sel:[1,1,1] ; encoding: [0x05,0x58,0x34,0xd5,0x01,0xff,0x03,0x00]
-v_subrev_f16 v5, v255, v2
-// GFX11: v_subrev_f16_e64 v5, v255, v2 ; encoding: [0x05,0x00,0x34,0xd5,0xff,0x05,0x02,0x00]
+v_subrev_f16 v5.h, v1.h, v255.h dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: v_subrev_f16_e64_dpp v5.h, v1.h, v255.h op_sel:[1,1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x58,0x34,0xd5,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05]
-v_subrev_f16 v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0]
-// GFX11: v_subrev_f16_e64_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x34,0xd5,0xe9,0x04,0x02,0x00,0xff,0x77,0x39,0x05]
+v_subrev_f16 v5.h, v1.h, v255.h quad_perm:[3,2,1,0]
+// GFX11: v_subrev_f16_e64_dpp v5.h, v1.h, v255.h op_sel:[1,1,1] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x58,0x34,0xd5,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff]
-v_subrev_f16 v5, v255, v2 quad_perm:[3,2,1,0]
-// GFX11: v_subrev_f16_e64_dpp v5, v255, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0xff,0x1b,0x00,0xff]
+v_subrev_f16 v5.h, v255.h, v2.h
+// GFX11: v_subrev_f16_e64 v5.h, v255.h, v2.h op_sel:[1,1,1] ; encoding: [0x05,0x58,0x34,0xd5,0xff,0x05,0x02,0x00]
+
+v_subrev_f16 v5.h, v255.h, v2.h dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: v_subrev_f16_e64_dpp v5.h, v255.h, v2.h op_sel:[1,1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x58,0x34,0xd5,0xe9,0x04,0x02,0x00,0xff,0x77,0x39,0x05]
+
+v_subrev_f16 v5.h, v255.h, v2.h quad_perm:[3,2,1,0]
+// GFX11: v_subrev_f16_e64_dpp v5.h, v255.h, v2.h op_sel:[1,1,1] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x58,0x34,0xd5,0xfa,0x04,0x02,0x00,0xff,0x1b,0x00,0xff]
+
+v_subrev_f16 v5.l, v1.l, v255.l
+// GFX11: v_subrev_f16_e64 v5.l, v1.l, v255.l ; encoding: [0x05,0x00,0x34,0xd5,0x01,0xff,0x03,0x00]
+
+v_subrev_f16 v5.l, v1.l, v255.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: v_subrev_f16_e64_dpp v5.l, v1.l, v255.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x34,0xd5,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05]
+
+v_subrev_f16 v5.l, v1.l, v255.l quad_perm:[3,2,1,0]
+// GFX11: v_subrev_f16_e64_dpp v5.l, v1.l, v255.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff]
+
+v_subrev_f16 v5.l, v255.l, v2.l
+// GFX11: v_subrev_f16_e64 v5.l, v255.l, v2.l ; encoding: [0x05,0x00,0x34,0xd5,0xff,0x05,0x02,0x00]
+
+v_subrev_f16 v5.l, v255.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: v_subrev_f16_e64_dpp v5.l, v255.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x34,0xd5,0xe9,0x04,0x02,0x00,0xff,0x77,0x39,0x05]
+
+v_subrev_f16 v5.l, v255.l, v2.l quad_perm:[3,2,1,0]
+// GFX11: v_subrev_f16_e64_dpp v5.l, v255.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0xff,0x1b,0x00,0xff]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vop2.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vop2.s
index 11d51bf696cd82..15d6547a04770c 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vop2.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vop2.s
@@ -1848,47 +1848,59 @@ v_subrev_co_ci_u32_e64_dpp v5, ttmp[14:15], v1, v2, ttmp[14:15] row_xmask:0 row_
v_subrev_co_ci_u32_e64_dpp v255, null, v255, v255, null clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
// GFX11: v_subrev_co_ci_u32_e64_dpp v255, null, v255, v255, null clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xff,0xfc,0x22,0xd5,0xfa,0xfe,0xf3,0x01,0xff,0x6f,0x05,0x30]
-v_subrev_f16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
-// GFX11: v_subrev_f16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+v_subrev_f16_e64_dpp v5.l, v1.l, v2.l quad_perm:[3,2,1,0]
+// GFX11: v_subrev_f16_e64_dpp v5.l, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
-v_subrev_f16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
-// GFX11: v_subrev_f16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+v_subrev_f16_e64_dpp v5.l, v1.l, v2.l quad_perm:[0,1,2,3]
+// GFX11: v_subrev_f16_e64_dpp v5.l, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
-v_subrev_f16_e64_dpp v5, v1, v2 row_mirror
-// GFX11: v_subrev_f16_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+v_subrev_f16_e64_dpp v5.l, v1.l, v2.l row_mirror
+// GFX11: v_subrev_f16_e64_dpp v5.l, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
-v_subrev_f16_e64_dpp v5, v1, v2 row_half_mirror
-// GFX11: v_subrev_f16_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+v_subrev_f16_e64_dpp v5.l, v1.l, v2.l row_half_mirror
+// GFX11: v_subrev_f16_e64_dpp v5.l, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
-v_subrev_f16_e64_dpp v5, v1, v2 row_shl:1
-// GFX11: v_subrev_f16_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+v_subrev_f16_e64_dpp v5.l, v1.l, v2.l row_shl:1
+// GFX11: v_subrev_f16_e64_dpp v5.l, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
-v_subrev_f16_e64_dpp v5, v1, v2 row_shl:15
-// GFX11: v_subrev_f16_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+v_subrev_f16_e64_dpp v5.l, v1.l, v2.l row_shl:15
+// GFX11: v_subrev_f16_e64_dpp v5.l, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
-v_subrev_f16_e64_dpp v5, v1, v2 row_shr:1
-// GFX11: v_subrev_f16_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+v_subrev_f16_e64_dpp v5.l, v1.l, v2.l row_shr:1
+// GFX11: v_subrev_f16_e64_dpp v5.l, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
-v_subrev_f16_e64_dpp v5, v1, v2 row_shr:15
-// GFX11: v_subrev_f16_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+v_subrev_f16_e64_dpp v5.l, v1.l, v2.l row_shr:15
+// GFX11: v_subrev_f16_e64_dpp v5.l, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
-v_subrev_f16_e64_dpp v5, v1, v2 row_ror:1
-// GFX11: v_subrev_f16_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+v_subrev_f16_e64_dpp v5.l, v1.l, v2.l row_ror:1
+// GFX11: v_subrev_f16_e64_dpp v5.l, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
-v_subrev_f16_e64_dpp v5, v1, v2 row_ror:15
-// GFX11: v_subrev_f16_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+v_subrev_f16_e64_dpp v5.l, v1.l, v2.l row_ror:15
+// GFX11: v_subrev_f16_e64_dpp v5.l, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
-v_subrev_f16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
-// GFX11: v_subrev_f16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+v_subrev_f16_e64_dpp v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf
+// GFX11: v_subrev_f16_e64_dpp v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
-v_subrev_f16_e64_dpp v5, |v1|, -v2 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
-// GFX11: v_subrev_f16_e64_dpp v5, |v1|, -v2 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x01,0x34,0xd5,0xfa,0x04,0x02,0x48,0x01,0x5f,0x01,0x01]
+v_subrev_f16_e64_dpp v5.l, |v1.l|, -v2.l mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX11: v_subrev_f16_e64_dpp v5.l, |v1.l|, -v2.l mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x01,0x34,0xd5,0xfa,0x04,0x02,0x48,0x01,0x5f,0x01,0x01]
-v_subrev_f16_e64_dpp v5, -v1, |v2| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
-// GFX11: v_subrev_f16_e64_dpp v5, -v1, |v2| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x05,0x02,0x34,0xd5,0xfa,0x04,0x02,0x30,0x01,0x60,0x09,0x13]
+v_subrev_f16_e64_dpp v5.l, -v1.l, |v2.l| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX11: v_subrev_f16_e64_dpp v5.l, -v1.l, |v2.l| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x05,0x02,0x34,0xd5,0xfa,0x04,0x02,0x30,0x01,0x60,0x09,0x13]
-v_subrev_f16_e64_dpp v255, -|v255|, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
-// GFX11: v_subrev_f16_e64_dpp v255, -|v255|, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xff,0x83,0x34,0xd5,0xfa,0xfe,0x03,0x78,0xff,0x6f,0x05,0x30]
+v_subrev_f16_e64_dpp v255.l, -|v255.l|, -|v255.l| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX11: v_subrev_f16_e64_dpp v255.l, -|v255.l|, -|v255.l| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xff,0x83,0x34,0xd5,0xfa,0xfe,0x03,0x78,0xff,0x6f,0x05,0x30]
+
+v_subrev_f16_e64_dpp v5.h, v1.h, v2.h row_share:0 row_mask:0xf bank_mask:0xf
+// GFX11: v_subrev_f16_e64_dpp v5.h, v1.h, v2.h op_sel:[1,1,1] row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x58,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_subrev_f16_e64_dpp v5.l, |v1.h|, -v2.l mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX11: v_subrev_f16_e64_dpp v5.l, |v1.h|, -v2.l op_sel:[1,0,0] mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x09,0x34,0xd5,0xfa,0x04,0x02,0x48,0x01,0x5f,0x01,0x01]
+
+v_subrev_f16_e64_dpp v5.l, -v1.l, |v2.h| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX11: v_subrev_f16_e64_dpp v5.l, -v1.l, |v2.h| op_sel:[0,1,0] mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x05,0x12,0x34,0xd5,0xfa,0x04,0x02,0x30,0x01,0x60,0x09,0x13]
+
+v_subrev_f16_e64_dpp v255.h, -|v255.l|, -|v255.l| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX11: v_subrev_f16_e64_dpp v255.h, -|v255.l|, -|v255.l| op_sel:[0,0,1] clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xff,0xc3,0x34,0xd5,0xfa,0xfe,0x03,0x78,0xff,0x6f,0x05,0x30]
v_subrev_f32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
// GFX11: v_subrev_f32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x05,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vop2.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vop2.s
index da4048ff3d1a40..2f52b7f467e000 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vop2.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vop2.s
@@ -571,17 +571,29 @@ v_subrev_co_ci_u32_e64_dpp v5, ttmp[14:15], v1, v2, ttmp[14:15] dpp8:[7,6,5,4,3,
v_subrev_co_ci_u32_e64_dpp v255, null, v255, v255, null clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
// GFX11: v_subrev_co_ci_u32_e64_dpp v255, null, v255, v255, null clamp dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xff,0xfc,0x22,0xd5,0xe9,0xfe,0xf3,0x01,0xff,0x00,0x00,0x00]
-v_subrev_f16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
-// GFX11: v_subrev_f16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x34,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+v_subrev_f16_e64_dpp v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: v_subrev_f16_e64_dpp v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x34,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
-v_subrev_f16_e64_dpp v5, |v1|, -v2 mul:2 dpp8:[7,6,5,4,3,2,1,0]
-// GFX11: v_subrev_f16_e64_dpp v5, |v1|, -v2 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x34,0xd5,0xe9,0x04,0x02,0x48,0x01,0x77,0x39,0x05]
+v_subrev_f16_e64_dpp v5.l, |v1.l|, -v2.l mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: v_subrev_f16_e64_dpp v5.l, |v1.l|, -v2.l mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x34,0xd5,0xe9,0x04,0x02,0x48,0x01,0x77,0x39,0x05]
-v_subrev_f16_e64_dpp v5, -v1, |v2| mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
-// GFX11: v_subrev_f16_e64_dpp v5, -v1, |v2| mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x05,0x02,0x34,0xd5,0xea,0x04,0x02,0x30,0x01,0x77,0x39,0x05]
+v_subrev_f16_e64_dpp v5.l, -v1.l, |v2.l| mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX11: v_subrev_f16_e64_dpp v5.l, -v1.l, |v2.l| mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x05,0x02,0x34,0xd5,0xea,0x04,0x02,0x30,0x01,0x77,0x39,0x05]
-v_subrev_f16_e64_dpp v255, -|v255|, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
-// GFX11: v_subrev_f16_e64_dpp v255, -|v255|, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xff,0x83,0x34,0xd5,0xe9,0xfe,0x03,0x78,0xff,0x00,0x00,0x00]
+v_subrev_f16_e64_dpp v255.l, -|v255.l|, -|v255.l| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX11: v_subrev_f16_e64_dpp v255.l, -|v255.l|, -|v255.l| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xff,0x83,0x34,0xd5,0xe9,0xfe,0x03,0x78,0xff,0x00,0x00,0x00]
+
+v_subrev_f16_e64_dpp v5.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: v_subrev_f16_e64_dpp v5.h, v1.h, v2.h op_sel:[1,1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x58,0x34,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_subrev_f16_e64_dpp v5.l, |v1.h|, -v2.l mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: v_subrev_f16_e64_dpp v5.l, |v1.h|, -v2.l op_sel:[1,0,0] mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x09,0x34,0xd5,0xe9,0x04,0x02,0x48,0x01,0x77,0x39,0x05]
+
+v_subrev_f16_e64_dpp v5.l, -v1.l, |v2.h| mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX11: v_subrev_f16_e64_dpp v5.l, -v1.l, |v2.h| op_sel:[0,1,0] mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x05,0x12,0x34,0xd5,0xea,0x04,0x02,0x30,0x01,0x77,0x39,0x05]
+
+v_subrev_f16_e64_dpp v255.h, -|v255.l|, -|v255.l| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX11: v_subrev_f16_e64_dpp v255.h, -|v255.l|, -|v255.l| op_sel:[0,0,1] clamp div:2 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xff,0xc3,0x34,0xd5,0xe9,0xfe,0x03,0x78,0xff,0x00,0x00,0x00]
v_subrev_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
// GFX11: v_subrev_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x05,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vop2.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vop2.s
index 48a6e7e8a8554e..5debd064812c36 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vop2.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vop2.s
@@ -2016,50 +2016,59 @@ v_subrev_co_ci_u32_e64 v5, ttmp[14:15], src_scc, null, ttmp[14:15]
v_subrev_co_ci_u32_e64 v255, null, 0xaf123456, vcc_hi, null clamp
// GFX11: v_subrev_co_ci_u32_e64 v255, null, 0xaf123456, vcc_hi, null clamp ; encoding: [0xff,0xfc,0x22,0xd5,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
-v_subrev_f16_e64 v5, v1, v2
-// GFX11: v_subrev_f16_e64 v5, v1, v2 ; encoding: [0x05,0x00,0x34,0xd5,0x01,0x05,0x02,0x00]
+v_subrev_f16_e64 v5.l, v1.l, v2.l
+// GFX11: v_subrev_f16_e64 v5.l, v1.l, v2.l ; encoding: [0x05,0x00,0x34,0xd5,0x01,0x05,0x02,0x00]
-v_subrev_f16_e64 v5, v255, v255
-// GFX11: v_subrev_f16_e64 v5, v255, v255 ; encoding: [0x05,0x00,0x34,0xd5,0xff,0xff,0x03,0x00]
+v_subrev_f16_e64 v5.l, v255.l, v255.l
+// GFX11: v_subrev_f16_e64 v5.l, v255.l, v255.l ; encoding: [0x05,0x00,0x34,0xd5,0xff,0xff,0x03,0x00]
-v_subrev_f16_e64 v5, s1, s2
-// GFX11: v_subrev_f16_e64 v5, s1, s2 ; encoding: [0x05,0x00,0x34,0xd5,0x01,0x04,0x00,0x00]
+v_subrev_f16_e64 v5.l, s1, s2
+// GFX11: v_subrev_f16_e64 v5.l, s1, s2 ; encoding: [0x05,0x00,0x34,0xd5,0x01,0x04,0x00,0x00]
-v_subrev_f16_e64 v5, s105, s105
-// GFX11: v_subrev_f16_e64 v5, s105, s105 ; encoding: [0x05,0x00,0x34,0xd5,0x69,0xd2,0x00,0x00]
+v_subrev_f16_e64 v5.l, s105, s105
+// GFX11: v_subrev_f16_e64 v5.l, s105, s105 ; encoding: [0x05,0x00,0x34,0xd5,0x69,0xd2,0x00,0x00]
-v_subrev_f16_e64 v5, vcc_lo, ttmp15
-// GFX11: v_subrev_f16_e64 v5, vcc_lo, ttmp15 ; encoding: [0x05,0x00,0x34,0xd5,0x6a,0xf6,0x00,0x00]
+v_subrev_f16_e64 v5.l, vcc_lo, ttmp15
+// GFX11: v_subrev_f16_e64 v5.l, vcc_lo, ttmp15 ; encoding: [0x05,0x00,0x34,0xd5,0x6a,0xf6,0x00,0x00]
-v_subrev_f16_e64 v5, vcc_hi, 0xfe0b
-// GFX11: v_subrev_f16_e64 v5, vcc_hi, 0xfe0b ; encoding: [0x05,0x00,0x34,0xd5,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+v_subrev_f16_e64 v5.l, vcc_hi, 0xfe0b
+// GFX11: v_subrev_f16_e64 v5.l, vcc_hi, 0xfe0b ; encoding: [0x05,0x00,0x34,0xd5,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
-v_subrev_f16_e64 v5, ttmp15, src_scc
-// GFX11: v_subrev_f16_e64 v5, ttmp15, src_scc ; encoding: [0x05,0x00,0x34,0xd5,0x7b,0xfa,0x01,0x00]
+v_subrev_f16_e64 v5.l, ttmp15, src_scc
+// GFX11: v_subrev_f16_e64 v5.l, ttmp15, src_scc ; encoding: [0x05,0x00,0x34,0xd5,0x7b,0xfa,0x01,0x00]
-v_subrev_f16_e64 v5, m0, 0.5
-// GFX11: v_subrev_f16_e64 v5, m0, 0.5 ; encoding: [0x05,0x00,0x34,0xd5,0x7d,0xe0,0x01,0x00]
+v_subrev_f16_e64 v5.l, m0, 0.5
+// GFX11: v_subrev_f16_e64 v5.l, m0, 0.5 ; encoding: [0x05,0x00,0x34,0xd5,0x7d,0xe0,0x01,0x00]
-v_subrev_f16_e64 v5, exec_lo, -1
-// GFX11: v_subrev_f16_e64 v5, exec_lo, -1 ; encoding: [0x05,0x00,0x34,0xd5,0x7e,0x82,0x01,0x00]
+v_subrev_f16_e64 v5.l, exec_lo, -1
+// GFX11: v_subrev_f16_e64 v5.l, exec_lo, -1 ; encoding: [0x05,0x00,0x34,0xd5,0x7e,0x82,0x01,0x00]
-v_subrev_f16_e64 v5, |exec_hi|, null
-// GFX11: v_subrev_f16_e64 v5, |exec_hi|, null ; encoding: [0x05,0x01,0x34,0xd5,0x7f,0xf8,0x00,0x00]
+v_subrev_f16_e64 v5.l, |exec_hi|, null
+// GFX11: v_subrev_f16_e64 v5.l, |exec_hi|, null ; encoding: [0x05,0x01,0x34,0xd5,0x7f,0xf8,0x00,0x00]
-v_subrev_f16_e64 v5, null, exec_lo
-// GFX11: v_subrev_f16_e64 v5, null, exec_lo ; encoding: [0x05,0x00,0x34,0xd5,0x7c,0xfc,0x00,0x00]
+v_subrev_f16_e64 v5.l, null, exec_lo
+// GFX11: v_subrev_f16_e64 v5.l, null, exec_lo ; encoding: [0x05,0x00,0x34,0xd5,0x7c,0xfc,0x00,0x00]
-v_subrev_f16_e64 v5, -1, exec_hi
-// GFX11: v_subrev_f16_e64 v5, -1, exec_hi ; encoding: [0x05,0x00,0x34,0xd5,0xc1,0xfe,0x00,0x00]
+v_subrev_f16_e64 v5.l, -1, exec_hi
+// GFX11: v_subrev_f16_e64 v5.l, -1, exec_hi ; encoding: [0x05,0x00,0x34,0xd5,0xc1,0xfe,0x00,0x00]
-v_subrev_f16_e64 v5, 0.5, -m0 mul:2
-// GFX11: v_subrev_f16_e64 v5, 0.5, -m0 mul:2 ; encoding: [0x05,0x00,0x34,0xd5,0xf0,0xfa,0x00,0x48]
+v_subrev_f16_e64 v5.l, 0.5, -m0 mul:2
+// GFX11: v_subrev_f16_e64 v5.l, 0.5, -m0 mul:2 ; encoding: [0x05,0x00,0x34,0xd5,0xf0,0xfa,0x00,0x48]
-v_subrev_f16_e64 v5, -src_scc, |vcc_lo| mul:4
-// GFX11: v_subrev_f16_e64 v5, -src_scc, |vcc_lo| mul:4 ; encoding: [0x05,0x02,0x34,0xd5,0xfd,0xd4,0x00,0x30]
+v_subrev_f16_e64 v5.l, -src_scc, |vcc_lo| mul:4
+// GFX11: v_subrev_f16_e64 v5.l, -src_scc, |vcc_lo| mul:4 ; encoding: [0x05,0x02,0x34,0xd5,0xfd,0xd4,0x00,0x30]
-v_subrev_f16_e64 v255, -|0xfe0b|, -|vcc_hi| clamp div:2
-// GFX11: v_subrev_f16_e64 v255, -|0xfe0b|, -|vcc_hi| clamp div:2 ; encoding: [0xff,0x83,0x34,0xd5,0xff,0xd6,0x00,0x78,0x0b,0xfe,0x00,0x00]
+v_subrev_f16_e64 v255.l, -|0xfe0b|, -|vcc_hi| clamp div:2
+// GFX11: v_subrev_f16_e64 v255.l, -|0xfe0b|, -|vcc_hi| clamp div:2 ; encoding: [0xff,0x83,0x34,0xd5,0xff,0xd6,0x00,0x78,0x0b,0xfe,0x00,0x00]
+
+v_subrev_f16_e64 v5.l, v1.h, v2.l
+// GFX11: v_subrev_f16_e64 v5.l, v1.h, v2.l op_sel:[1,0,0] ; encoding: [0x05,0x08,0x34,0xd5,0x01,0x05,0x02,0x00]
+
+v_subrev_f16_e64 v5.l, v255.l, v255.h
+// GFX11: v_subrev_f16_e64 v5.l, v255.l, v255.h op_sel:[0,1,0] ; encoding: [0x05,0x10,0x34,0xd5,0xff,0xff,0x03,0x00]
+
+v_subrev_f16_e64 v255.h, -|0xfe0b|, -|vcc_hi| clamp div:2
+// GFX11: v_subrev_f16_e64 v255.h, -|0xfe0b|, -|vcc_hi| op_sel:[0,0,1] clamp div:2 ; encoding: [0xff,0xc3,0x34,0xd5,0xff,0xd6,0x00,0x78,0x0b,0xfe,0x00,0x00]
v_subrev_f32_e64 v5, v1, v2
// GFX11: v_subrev_f32_e64 v5, v1, v2 ; encoding: [0x05,0x00,0x05,0xd5,0x01,0x05,0x02,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop2.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop2.s
index 1191801972b778..6230fbac358985 100644
--- a/llvm/test/MC/AMDGPU/gfx12_asm_vop2.s
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop2.s
@@ -2419,50 +2419,62 @@ v_subrev_co_ci_u32 v255, vcc, 0xaf123456, v255, vcc
// W64: v_subrev_co_ci_u32_e32 v255, vcc, 0xaf123456, v255, vcc ; encoding: [0xff,0xfe,0xff,0x45,0x56,0x34,0x12,0xaf]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_subrev_f16 v5, v1, v2
-// GFX12: v_subrev_f16_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x68]
+v_subrev_f16 v5.l, v1.l, v2.l
+// GFX12: v_subrev_f16_e32 v5.l, v1.l, v2.l ; encoding: [0x01,0x05,0x0a,0x68]
-v_subrev_f16 v5, v127, v2
-// GFX12: v_subrev_f16_e32 v5, v127, v2 ; encoding: [0x7f,0x05,0x0a,0x68]
+v_subrev_f16 v5.l, v127.l, v2.l
+// GFX12: v_subrev_f16_e32 v5.l, v127.l, v2.l ; encoding: [0x7f,0x05,0x0a,0x68]
-v_subrev_f16 v5, s1, v2
-// GFX12: v_subrev_f16_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x68]
+v_subrev_f16 v5.l, s1, v2.l
+// GFX12: v_subrev_f16_e32 v5.l, s1, v2.l ; encoding: [0x01,0x04,0x0a,0x68]
-v_subrev_f16 v5, s105, v2
-// GFX12: v_subrev_f16_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x68]
+v_subrev_f16 v5.l, s105, v2.l
+// GFX12: v_subrev_f16_e32 v5.l, s105, v2.l ; encoding: [0x69,0x04,0x0a,0x68]
-v_subrev_f16 v5, vcc_lo, v2
-// GFX12: v_subrev_f16_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x68]
+v_subrev_f16 v5.l, vcc_lo, v2.l
+// GFX12: v_subrev_f16_e32 v5.l, vcc_lo, v2.l ; encoding: [0x6a,0x04,0x0a,0x68]
-v_subrev_f16 v5, vcc_hi, v2
-// GFX12: v_subrev_f16_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x68]
+v_subrev_f16 v5.l, vcc_hi, v2.l
+// GFX12: v_subrev_f16_e32 v5.l, vcc_hi, v2.l ; encoding: [0x6b,0x04,0x0a,0x68]
-v_subrev_f16 v5, ttmp15, v2
-// GFX12: v_subrev_f16_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x68]
+v_subrev_f16 v5.l, ttmp15, v2.l
+// GFX12: v_subrev_f16_e32 v5.l, ttmp15, v2.l ; encoding: [0x7b,0x04,0x0a,0x68]
-v_subrev_f16 v5, m0, v2
-// GFX12: v_subrev_f16_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x68]
+v_subrev_f16 v5.l, m0, v2.l
+// GFX12: v_subrev_f16_e32 v5.l, m0, v2.l ; encoding: [0x7d,0x04,0x0a,0x68]
-v_subrev_f16 v5, exec_lo, v2
-// GFX12: v_subrev_f16_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x68]
+v_subrev_f16 v5.l, exec_lo, v2.l
+// GFX12: v_subrev_f16_e32 v5.l, exec_lo, v2.l ; encoding: [0x7e,0x04,0x0a,0x68]
-v_subrev_f16 v5, exec_hi, v2
-// GFX12: v_subrev_f16_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x68]
+v_subrev_f16 v5.l, exec_hi, v2.l
+// GFX12: v_subrev_f16_e32 v5.l, exec_hi, v2.l ; encoding: [0x7f,0x04,0x0a,0x68]
-v_subrev_f16 v5, null, v2
-// GFX12: v_subrev_f16_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x68]
+v_subrev_f16 v5.l, null, v2.l
+// GFX12: v_subrev_f16_e32 v5.l, null, v2.l ; encoding: [0x7c,0x04,0x0a,0x68]
-v_subrev_f16 v5, -1, v2
-// GFX12: v_subrev_f16_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x68]
+v_subrev_f16 v5.l, -1, v2.l
+// GFX12: v_subrev_f16_e32 v5.l, -1, v2.l ; encoding: [0xc1,0x04,0x0a,0x68]
-v_subrev_f16 v5, 0.5, v2
-// GFX12: v_subrev_f16_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x68]
+v_subrev_f16 v5.l, 0.5, v2.l
+// GFX12: v_subrev_f16_e32 v5.l, 0.5, v2.l ; encoding: [0xf0,0x04,0x0a,0x68]
-v_subrev_f16 v5, src_scc, v2
-// GFX12: v_subrev_f16_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x68]
+v_subrev_f16 v5.l, src_scc, v2.l
+// GFX12: v_subrev_f16_e32 v5.l, src_scc, v2.l ; encoding: [0xfd,0x04,0x0a,0x68]
-v_subrev_f16 v127, 0xfe0b, v127
-// GFX12: v_subrev_f16_e32 v127, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfe,0x68,0x0b,0xfe,0x00,0x00]
+v_subrev_f16 v127.l, 0xfe0b, v127.l
+// GFX12: v_subrev_f16_e32 v127.l, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0xfe,0x68,0x0b,0xfe,0x00,0x00]
+
+v_subrev_f16 v5.l, v1.h, v2.l
+// GFX12: v_subrev_f16_e32 v5.l, v1.h, v2.l ; encoding: [0x81,0x05,0x0a,0x68]
+
+v_subrev_f16 v5.l, v127.h, v2.l
+// GFX12: v_subrev_f16_e32 v5.l, v127.h, v2.l ; encoding: [0xff,0x05,0x0a,0x68]
+
+v_subrev_f16 v5.h, src_scc, v2.h
+// GFX12: v_subrev_f16_e32 v5.h, src_scc, v2.h ; encoding: [0xfd,0x04,0x0b,0x69]
+
+v_subrev_f16 v127.h, 0xfe0b, v127.h
+// GFX12: v_subrev_f16_e32 v127.h, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0xff,0x69,0x0b,0xfe,0x00,0x00]
v_subrev_f32 v5, v1, v2
// GFX12: v_subrev_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x0a]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp16.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp16.s
index 0b4212cc0dd9b0..c9f05df0e7c02a 100644
--- a/llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp16.s
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp16.s
@@ -1784,47 +1784,53 @@ v_subrev_co_ci_u32 v255, vcc, v255, v255, vcc row_xmask:15 row_mask:0x3 bank_mas
// W64: v_subrev_co_ci_u32_dpp v255, vcc, v255, v255, vcc row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x45,0xff,0x6f,0x05,0x30]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_subrev_f16 v5, v1, v2 quad_perm:[3,2,1,0]
-// GFX12: v_subrev_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x1b,0x00,0xff]
+v_subrev_f16 v5.l, v1.l, v2.l quad_perm:[3,2,1,0]
+// GFX12: v_subrev_f16_dpp v5.l, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x1b,0x00,0xff]
-v_subrev_f16 v5, v1, v2 quad_perm:[0,1,2,3]
-// GFX12: v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0xff]
+v_subrev_f16 v5.l, v1.l, v2.l quad_perm:[0,1,2,3]
+// GFX12: v_subrev_f16_dpp v5.l, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0xff]
-v_subrev_f16 v5, v1, v2 row_mirror
-// GFX12: v_subrev_f16_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x40,0x01,0xff]
+v_subrev_f16 v5.l, v1.l, v2.l row_mirror
+// GFX12: v_subrev_f16_dpp v5.l, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x40,0x01,0xff]
-v_subrev_f16 v5, v1, v2 row_half_mirror
-// GFX12: v_subrev_f16_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x41,0x01,0xff]
+v_subrev_f16 v5.l, v1.l, v2.l row_half_mirror
+// GFX12: v_subrev_f16_dpp v5.l, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x41,0x01,0xff]
-v_subrev_f16 v5, v1, v2 row_shl:1
-// GFX12: v_subrev_f16_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x01,0x01,0xff]
+v_subrev_f16 v5.l, v1.l, v2.l row_shl:1
+// GFX12: v_subrev_f16_dpp v5.l, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x01,0x01,0xff]
-v_subrev_f16 v5, v1, v2 row_shl:15
-// GFX12: v_subrev_f16_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x0f,0x01,0xff]
+v_subrev_f16 v5.l, v1.l, v2.l row_shl:15
+// GFX12: v_subrev_f16_dpp v5.l, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x0f,0x01,0xff]
-v_subrev_f16 v5, v1, v2 row_shr:1
-// GFX12: v_subrev_f16_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x11,0x01,0xff]
+v_subrev_f16 v5.l, v1.l, v2.l row_shr:1
+// GFX12: v_subrev_f16_dpp v5.l, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x11,0x01,0xff]
-v_subrev_f16 v5, v1, v2 row_shr:15
-// GFX12: v_subrev_f16_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x1f,0x01,0xff]
+v_subrev_f16 v5.l, v1.l, v2.l row_shr:15
+// GFX12: v_subrev_f16_dpp v5.l, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x1f,0x01,0xff]
-v_subrev_f16 v5, v1, v2 row_ror:1
-// GFX12: v_subrev_f16_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x21,0x01,0xff]
+v_subrev_f16 v5.l, v1.l, v2.l row_ror:1
+// GFX12: v_subrev_f16_dpp v5.l, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x21,0x01,0xff]
-v_subrev_f16 v5, v1, v2 row_ror:15
-// GFX12: v_subrev_f16_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x2f,0x01,0xff]
+v_subrev_f16 v5.l, v1.l, v2.l row_ror:15
+// GFX12: v_subrev_f16_dpp v5.l, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x2f,0x01,0xff]
-v_subrev_f16 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
-// GFX12: v_subrev_f16_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x50,0x01,0xff]
+v_subrev_f16 v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: v_subrev_f16_dpp v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x50,0x01,0xff]
-v_subrev_f16 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
-// GFX12: v_subrev_f16_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x5f,0x01,0x01]
+v_subrev_f16 v5.l, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: v_subrev_f16_dpp v5.l, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x5f,0x01,0x01]
-v_subrev_f16 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
-// GFX12: v_subrev_f16_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x60,0x09,0x13]
+v_subrev_f16 v5.l, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: v_subrev_f16_dpp v5.l, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x60,0x09,0x13]
-v_subrev_f16 v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
-// GFX12: v_subrev_f16_dpp v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x68,0x7f,0x6f,0xf5,0x30]
+v_subrev_f16 v127.l, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: v_subrev_f16_dpp v127.l, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x68,0x7f,0x6f,0xf5,0x30]
+
+v_subrev_f16 v5.h, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: v_subrev_f16_dpp v5.h, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0b,0x69,0x81,0x60,0x09,0x13]
+
+v_subrev_f16 v127.h, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: v_subrev_f16_dpp v127.h, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x69,0xff,0x6f,0xf5,0x30]
v_subrev_f32 v5, v1, v2 quad_perm:[3,2,1,0]
// GFX12: v_subrev_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x1b,0x00,0xff]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp8.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp8.s
index 956733742e3337..0063b53fe743c0 100644
--- a/llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp8.s
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp8.s
@@ -409,14 +409,20 @@ v_subrev_co_ci_u32 v255, vcc, v255, v255, vcc dpp8:[0,0,0,0,0,0,0,0] fi:0
// W64: v_subrev_co_ci_u32_dpp v255, vcc, v255, v255, vcc dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0xff,0x45,0xff,0x00,0x00,0x00]
// W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
-v_subrev_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
-// GFX12: v_subrev_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x68,0x01,0x77,0x39,0x05]
+v_subrev_f16 v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_subrev_f16_dpp v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x68,0x01,0x77,0x39,0x05]
-v_subrev_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
-// GFX12: v_subrev_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x0a,0x68,0x01,0x77,0x39,0x05]
+v_subrev_f16 v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: v_subrev_f16_dpp v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x0a,0x68,0x01,0x77,0x39,0x05]
-v_subrev_f16 v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
-// GFX12: v_subrev_f16_dpp v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0xfe,0x68,0x7f,0x00,0x00,0x00]
+v_subrev_f16 v127.l, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: v_subrev_f16_dpp v127.l, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0xfe,0x68,0x7f,0x00,0x00,0x00]
+
+v_subrev_f16 v5.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: v_subrev_f16_dpp v5.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x0b,0x69,0x81,0x77,0x39,0x05]
+
+v_subrev_f16 v127.h, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: v_subrev_f16_dpp v127.h, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xfe,0xff,0x69,0xff,0x00,0x00,0x00]
v_subrev_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
// GFX12: v_subrev_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x0a,0x01,0x77,0x39,0x05]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_err.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_err.s
index 862845071d2743..82c4518082da88 100644
--- a/llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_err.s
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_err.s
@@ -352,29 +352,56 @@ v_sub_f16_e32 v5.l, v1.l, v255.l
v_sub_f16_e32 v5.l, v255.l, v2.l
// GFX12: :[[@LINE-1]]:21: error: invalid operand for instruction
-v_subrev_f16_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
-// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_subrev_f16_dpp v255.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:18: error: invalid operand for instruction
-v_subrev_f16_dpp v255, v1, v2 quad_perm:[3,2,1,0]
-// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_subrev_f16_dpp v255.h, v1.h, v2.h quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:18: error: invalid operand for instruction
-v_subrev_f16_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
-// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_subrev_f16_dpp v255.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:18: error: invalid operand for instruction
-v_subrev_f16_dpp v5, v1, v255 quad_perm:[3,2,1,0]
-// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_subrev_f16_dpp v255.l, v1.l, v2.l quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:18: error: invalid operand for instruction
-v_subrev_f16_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0]
-// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_subrev_f16_dpp v5.h, v1.h, v255.h dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:30: error: invalid operand for instruction
-v_subrev_f16_dpp v5, v255, v2 quad_perm:[3,2,1,0]
-// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_subrev_f16_dpp v5.h, v1.h, v255.h quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:30: error: invalid operand for instruction
-v_subrev_f16_e32 v255, v1, v2
-// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_subrev_f16_dpp v5.h, v255.h, v2.h dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:24: error: invalid operand for instruction
-v_subrev_f16_e32 v5, v1, v255
-// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_subrev_f16_dpp v5.h, v255.h, v2.h quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:24: error: invalid operand for instruction
-v_subrev_f16_e32 v5, v255, v2
-// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_subrev_f16_dpp v5.l, v1.l, v255.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:30: error: invalid operand for instruction
+
+v_subrev_f16_dpp v5.l, v1.l, v255.l quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:30: error: invalid operand for instruction
+
+v_subrev_f16_dpp v5.l, v255.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:24: error: invalid operand for instruction
+
+v_subrev_f16_dpp v5.l, v255.l, v2.l quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:24: error: invalid operand for instruction
+
+v_subrev_f16_e32 v255.h, v1.h, v2.h
+// GFX12: :[[@LINE-1]]:18: error: invalid operand for instruction
+
+v_subrev_f16_e32 v255.l, v1.l, v2.l
+// GFX12: :[[@LINE-1]]:18: error: invalid operand for instruction
+
+v_subrev_f16_e32 v5.h, v1.h, v255.h
+// GFX12: :[[@LINE-1]]:30: error: invalid operand for instruction
+
+v_subrev_f16_e32 v5.h, v255.h, v2.h
+// GFX12: :[[@LINE-1]]:24: error: invalid operand for instruction
+
+v_subrev_f16_e32 v5.l, v1.l, v255.l
+// GFX12: :[[@LINE-1]]:30: error: invalid operand for instruction
+
+v_subrev_f16_e32 v5.l, v255.l, v2.l
+// GFX12: :[[@LINE-1]]:24: error: invalid operand for instruction
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_promote.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_promote.s
index 73c9e8f2134398..e1286dadfb6e16 100644
--- a/llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_promote.s
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_promote.s
@@ -271,29 +271,56 @@ v_sub_f16 v5.l, v255.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
v_sub_f16 v5.l, v255.l, v2.l quad_perm:[3,2,1,0]
// GFX12: v_sub_f16_e64_dpp v5.l, v255.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x33,0xd5,0xfa,0x04,0x02,0x00,0xff,0x1b,0x00,0xff]
-v_subrev_f16 v255, v1, v2
-// GFX12: v_subrev_f16_e64 v255, v1, v2 ; encoding: [0xff,0x00,0x34,0xd5,0x01,0x05,0x02,0x00]
+v_subrev_f16 v255.h, v1.h, v2.h
+// GFX12: v_subrev_f16_e64 v255.h, v1.h, v2.h op_sel:[1,1,1] ; encoding: [0xff,0x58,0x34,0xd5,0x01,0x05,0x02,0x00]
-v_subrev_f16 v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
-// GFX12: v_subrev_f16_e64_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xff,0x00,0x34,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+v_subrev_f16 v255.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_subrev_f16_e64_dpp v255.h, v1.h, v2.h op_sel:[1,1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xff,0x58,0x34,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
-v_subrev_f16 v255, v1, v2 quad_perm:[3,2,1,0]
-// GFX12: v_subrev_f16_e64_dpp v255, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xff,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+v_subrev_f16 v255.h, v1.h, v2.h quad_perm:[3,2,1,0]
+// GFX12: v_subrev_f16_e64_dpp v255.h, v1.h, v2.h op_sel:[1,1,1] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xff,0x58,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
-v_subrev_f16 v5, v1, v255
-// GFX12: v_subrev_f16_e64 v5, v1, v255 ; encoding: [0x05,0x00,0x34,0xd5,0x01,0xff,0x03,0x00]
+v_subrev_f16 v255.l, v1.l, v2.l
+// GFX12: v_subrev_f16_e64 v255.l, v1.l, v2.l ; encoding: [0xff,0x00,0x34,0xd5,0x01,0x05,0x02,0x00]
-v_subrev_f16 v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0]
-// GFX12: v_subrev_f16_e64_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x34,0xd5,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05]
+v_subrev_f16 v255.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_subrev_f16_e64_dpp v255.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xff,0x00,0x34,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
-v_subrev_f16 v5, v1, v255 quad_perm:[3,2,1,0]
-// GFX12: v_subrev_f16_e64_dpp v5, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff]
+v_subrev_f16 v255.l, v1.l, v2.l quad_perm:[3,2,1,0]
+// GFX12: v_subrev_f16_e64_dpp v255.l, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xff,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
-v_subrev_f16 v5, v255, v2
-// GFX12: v_subrev_f16_e64 v5, v255, v2 ; encoding: [0x05,0x00,0x34,0xd5,0xff,0x05,0x02,0x00]
+v_subrev_f16 v5.h, v1.h, v255.h
+// GFX12: v_subrev_f16_e64 v5.h, v1.h, v255.h op_sel:[1,1,1] ; encoding: [0x05,0x58,0x34,0xd5,0x01,0xff,0x03,0x00]
-v_subrev_f16 v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0]
-// GFX12: v_subrev_f16_e64_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x34,0xd5,0xe9,0x04,0x02,0x00,0xff,0x77,0x39,0x05]
+v_subrev_f16 v5.h, v1.h, v255.h dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_subrev_f16_e64_dpp v5.h, v1.h, v255.h op_sel:[1,1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x58,0x34,0xd5,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05]
-v_subrev_f16 v5, v255, v2 quad_perm:[3,2,1,0]
-// GFX12: v_subrev_f16_e64_dpp v5, v255, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0xff,0x1b,0x00,0xff]
+v_subrev_f16 v5.h, v1.h, v255.h quad_perm:[3,2,1,0]
+// GFX12: v_subrev_f16_e64_dpp v5.h, v1.h, v255.h op_sel:[1,1,1] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x58,0x34,0xd5,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff]
+
+v_subrev_f16 v5.h, v255.h, v2.h
+// GFX12: v_subrev_f16_e64 v5.h, v255.h, v2.h op_sel:[1,1,1] ; encoding: [0x05,0x58,0x34,0xd5,0xff,0x05,0x02,0x00]
+
+v_subrev_f16 v5.h, v255.h, v2.h dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_subrev_f16_e64_dpp v5.h, v255.h, v2.h op_sel:[1,1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x58,0x34,0xd5,0xe9,0x04,0x02,0x00,0xff,0x77,0x39,0x05]
+
+v_subrev_f16 v5.h, v255.h, v2.h quad_perm:[3,2,1,0]
+// GFX12: v_subrev_f16_e64_dpp v5.h, v255.h, v2.h op_sel:[1,1,1] quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x58,0x34,0xd5,0xfa,0x04,0x02,0x00,0xff,0x1b,0x00,0xff]
+
+v_subrev_f16 v5.l, v1.l, v255.l
+// GFX12: v_subrev_f16_e64 v5.l, v1.l, v255.l ; encoding: [0x05,0x00,0x34,0xd5,0x01,0xff,0x03,0x00]
+
+v_subrev_f16 v5.l, v1.l, v255.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_subrev_f16_e64_dpp v5.l, v1.l, v255.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x34,0xd5,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05]
+
+v_subrev_f16 v5.l, v1.l, v255.l quad_perm:[3,2,1,0]
+// GFX12: v_subrev_f16_e64_dpp v5.l, v1.l, v255.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff]
+
+v_subrev_f16 v5.l, v255.l, v2.l
+// GFX12: v_subrev_f16_e64 v5.l, v255.l, v2.l ; encoding: [0x05,0x00,0x34,0xd5,0xff,0x05,0x02,0x00]
+
+v_subrev_f16 v5.l, v255.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_subrev_f16_e64_dpp v5.l, v255.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x34,0xd5,0xe9,0x04,0x02,0x00,0xff,0x77,0x39,0x05]
+
+v_subrev_f16 v5.l, v255.l, v2.l quad_perm:[3,2,1,0]
+// GFX12: v_subrev_f16_e64_dpp v5.l, v255.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0xff,0x1b,0x00,0xff]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2.s
index 59bc82169d0263..7674eafd9c30a1 100644
--- a/llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2.s
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2.s
@@ -2079,50 +2079,59 @@ v_subrev_co_ci_u32_e64 v5, ttmp[14:15], src_scc, null, ttmp[14:15]
v_subrev_co_ci_u32_e64 v255, null, 0xaf123456, vcc_hi, null clamp
// GFX12: v_subrev_co_ci_u32_e64 v255, null, 0xaf123456, vcc_hi, null clamp ; encoding: [0xff,0xfc,0x22,0xd5,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]
-v_subrev_f16_e64 v5, v1, v2
-// GFX12: v_subrev_f16_e64 v5, v1, v2 ; encoding: [0x05,0x00,0x34,0xd5,0x01,0x05,0x02,0x00]
+v_subrev_f16_e64 v5.l, v1.l, v2.l
+// GFX12: v_subrev_f16_e64 v5.l, v1.l, v2.l ; encoding: [0x05,0x00,0x34,0xd5,0x01,0x05,0x02,0x00]
-v_subrev_f16_e64 v5, v255, v255
-// GFX12: v_subrev_f16_e64 v5, v255, v255 ; encoding: [0x05,0x00,0x34,0xd5,0xff,0xff,0x03,0x00]
+v_subrev_f16_e64 v5.l, v255.l, v255.l
+// GFX12: v_subrev_f16_e64 v5.l, v255.l, v255.l ; encoding: [0x05,0x00,0x34,0xd5,0xff,0xff,0x03,0x00]
-v_subrev_f16_e64 v5, s1, s2
-// GFX12: v_subrev_f16_e64 v5, s1, s2 ; encoding: [0x05,0x00,0x34,0xd5,0x01,0x04,0x00,0x00]
+v_subrev_f16_e64 v5.l, s1, s2
+// GFX12: v_subrev_f16_e64 v5.l, s1, s2 ; encoding: [0x05,0x00,0x34,0xd5,0x01,0x04,0x00,0x00]
-v_subrev_f16_e64 v5, s105, s105
-// GFX12: v_subrev_f16_e64 v5, s105, s105 ; encoding: [0x05,0x00,0x34,0xd5,0x69,0xd2,0x00,0x00]
+v_subrev_f16_e64 v5.l, s105, s105
+// GFX12: v_subrev_f16_e64 v5.l, s105, s105 ; encoding: [0x05,0x00,0x34,0xd5,0x69,0xd2,0x00,0x00]
-v_subrev_f16_e64 v5, vcc_lo, ttmp15
-// GFX12: v_subrev_f16_e64 v5, vcc_lo, ttmp15 ; encoding: [0x05,0x00,0x34,0xd5,0x6a,0xf6,0x00,0x00]
+v_subrev_f16_e64 v5.l, vcc_lo, ttmp15
+// GFX12: v_subrev_f16_e64 v5.l, vcc_lo, ttmp15 ; encoding: [0x05,0x00,0x34,0xd5,0x6a,0xf6,0x00,0x00]
-v_subrev_f16_e64 v5, vcc_hi, 0xfe0b
-// GFX12: v_subrev_f16_e64 v5, vcc_hi, 0xfe0b ; encoding: [0x05,0x00,0x34,0xd5,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
+v_subrev_f16_e64 v5.l, vcc_hi, 0xfe0b
+// GFX12: v_subrev_f16_e64 v5.l, vcc_hi, 0xfe0b ; encoding: [0x05,0x00,0x34,0xd5,0x6b,0xfe,0x01,0x00,0x0b,0xfe,0x00,0x00]
-v_subrev_f16_e64 v5, ttmp15, src_scc
-// GFX12: v_subrev_f16_e64 v5, ttmp15, src_scc ; encoding: [0x05,0x00,0x34,0xd5,0x7b,0xfa,0x01,0x00]
+v_subrev_f16_e64 v5.l, ttmp15, src_scc
+// GFX12: v_subrev_f16_e64 v5.l, ttmp15, src_scc ; encoding: [0x05,0x00,0x34,0xd5,0x7b,0xfa,0x01,0x00]
-v_subrev_f16_e64 v5, m0, 0.5
-// GFX12: v_subrev_f16_e64 v5, m0, 0.5 ; encoding: [0x05,0x00,0x34,0xd5,0x7d,0xe0,0x01,0x00]
+v_subrev_f16_e64 v5.l, m0, 0.5
+// GFX12: v_subrev_f16_e64 v5.l, m0, 0.5 ; encoding: [0x05,0x00,0x34,0xd5,0x7d,0xe0,0x01,0x00]
-v_subrev_f16_e64 v5, exec_lo, -1
-// GFX12: v_subrev_f16_e64 v5, exec_lo, -1 ; encoding: [0x05,0x00,0x34,0xd5,0x7e,0x82,0x01,0x00]
+v_subrev_f16_e64 v5.l, exec_lo, -1
+// GFX12: v_subrev_f16_e64 v5.l, exec_lo, -1 ; encoding: [0x05,0x00,0x34,0xd5,0x7e,0x82,0x01,0x00]
-v_subrev_f16_e64 v5, |exec_hi|, null
-// GFX12: v_subrev_f16_e64 v5, |exec_hi|, null ; encoding: [0x05,0x01,0x34,0xd5,0x7f,0xf8,0x00,0x00]
+v_subrev_f16_e64 v5.l, |exec_hi|, null
+// GFX12: v_subrev_f16_e64 v5.l, |exec_hi|, null ; encoding: [0x05,0x01,0x34,0xd5,0x7f,0xf8,0x00,0x00]
-v_subrev_f16_e64 v5, null, exec_lo
-// GFX12: v_subrev_f16_e64 v5, null, exec_lo ; encoding: [0x05,0x00,0x34,0xd5,0x7c,0xfc,0x00,0x00]
+v_subrev_f16_e64 v5.l, null, exec_lo
+// GFX12: v_subrev_f16_e64 v5.l, null, exec_lo ; encoding: [0x05,0x00,0x34,0xd5,0x7c,0xfc,0x00,0x00]
-v_subrev_f16_e64 v5, -1, exec_hi
-// GFX12: v_subrev_f16_e64 v5, -1, exec_hi ; encoding: [0x05,0x00,0x34,0xd5,0xc1,0xfe,0x00,0x00]
+v_subrev_f16_e64 v5.l, -1, exec_hi
+// GFX12: v_subrev_f16_e64 v5.l, -1, exec_hi ; encoding: [0x05,0x00,0x34,0xd5,0xc1,0xfe,0x00,0x00]
-v_subrev_f16_e64 v5, 0.5, -m0 mul:2
-// GFX12: v_subrev_f16_e64 v5, 0.5, -m0 mul:2 ; encoding: [0x05,0x00,0x34,0xd5,0xf0,0xfa,0x00,0x48]
+v_subrev_f16_e64 v5.l, 0.5, -m0 mul:2
+// GFX12: v_subrev_f16_e64 v5.l, 0.5, -m0 mul:2 ; encoding: [0x05,0x00,0x34,0xd5,0xf0,0xfa,0x00,0x48]
-v_subrev_f16_e64 v5, -src_scc, |vcc_lo| mul:4
-// GFX12: v_subrev_f16_e64 v5, -src_scc, |vcc_lo| mul:4 ; encoding: [0x05,0x02,0x34,0xd5,0xfd,0xd4,0x00,0x30]
+v_subrev_f16_e64 v5.l, -src_scc, |vcc_lo| mul:4
+// GFX12: v_subrev_f16_e64 v5.l, -src_scc, |vcc_lo| mul:4 ; encoding: [0x05,0x02,0x34,0xd5,0xfd,0xd4,0x00,0x30]
-v_subrev_f16_e64 v255, -|0xfe0b|, -|vcc_hi| clamp div:2
-// GFX12: v_subrev_f16_e64 v255, -|0xfe0b|, -|vcc_hi| clamp div:2 ; encoding: [0xff,0x83,0x34,0xd5,0xff,0xd6,0x00,0x78,0x0b,0xfe,0x00,0x00]
+v_subrev_f16_e64 v255.l, -|0xfe0b|, -|vcc_hi| clamp div:2
+// GFX12: v_subrev_f16_e64 v255.l, -|0xfe0b|, -|vcc_hi| clamp div:2 ; encoding: [0xff,0x83,0x34,0xd5,0xff,0xd6,0x00,0x78,0x0b,0xfe,0x00,0x00]
+
+v_subrev_f16_e64 v5.l, v1.h, v2.l
+// GFX12: v_subrev_f16_e64 v5.l, v1.h, v2.l op_sel:[1,0,0] ; encoding: [0x05,0x08,0x34,0xd5,0x01,0x05,0x02,0x00]
+
+v_subrev_f16_e64 v5.l, v255.l, v255.h
+// GFX12: v_subrev_f16_e64 v5.l, v255.l, v255.h op_sel:[0,1,0] ; encoding: [0x05,0x10,0x34,0xd5,0xff,0xff,0x03,0x00]
+
+v_subrev_f16_e64 v255.h, -|0xfe0b|, -|vcc_hi| clamp div:2
+// GFX12: v_subrev_f16_e64 v255.h, -|0xfe0b|, -|vcc_hi| op_sel:[0,0,1] clamp div:2 ; encoding: [0xff,0xc3,0x34,0xd5,0xff,0xd6,0x00,0x78,0x0b,0xfe,0x00,0x00]
v_subrev_f32_e64 v5, v1, v2
// GFX12: v_subrev_f32_e64 v5, v1, v2 ; encoding: [0x05,0x00,0x05,0xd5,0x01,0x05,0x02,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2_dpp16.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2_dpp16.s
index 8a512b516a41ea..e27706ec02ea0d 100644
--- a/llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2_dpp16.s
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2_dpp16.s
@@ -1920,53 +1920,65 @@ v_subrev_co_ci_u32_e64_dpp v5, ttmp[14:15], v1, v2, ttmp[14:15] row_xmask:0 row_
v_subrev_co_ci_u32_e64_dpp v255, null, v255, v255, null clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
// GFX12: v_subrev_co_ci_u32_e64_dpp v255, null, v255, v255, null clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xff,0xfc,0x22,0xd5,0xfa,0xfe,0xf3,0x01,0xff,0x6f,0x05,0x30]
-v_subrev_f16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
-// GFX12: v_subrev_f16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
+v_subrev_f16_e64_dpp v5.l, v1.l, v2.l quad_perm:[3,2,1,0]
+// GFX12: v_subrev_f16_e64_dpp v5.l, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
-v_subrev_f16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3]
-// GFX12: v_subrev_f16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
+v_subrev_f16_e64_dpp v5.l, v1.l, v2.l quad_perm:[0,1,2,3]
+// GFX12: v_subrev_f16_e64_dpp v5.l, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
-v_subrev_f16_e64_dpp v5, v1, v2 row_mirror
-// GFX12: v_subrev_f16_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
+v_subrev_f16_e64_dpp v5.l, v1.l, v2.l row_mirror
+// GFX12: v_subrev_f16_e64_dpp v5.l, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
-v_subrev_f16_e64_dpp v5, v1, v2 row_half_mirror
-// GFX12: v_subrev_f16_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
+v_subrev_f16_e64_dpp v5.l, v1.l, v2.l row_half_mirror
+// GFX12: v_subrev_f16_e64_dpp v5.l, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
-v_subrev_f16_e64_dpp v5, v1, v2 row_shl:1
-// GFX12: v_subrev_f16_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
+v_subrev_f16_e64_dpp v5.l, v1.l, v2.l row_shl:1
+// GFX12: v_subrev_f16_e64_dpp v5.l, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
-v_subrev_f16_e64_dpp v5, v1, v2 row_shl:15
-// GFX12: v_subrev_f16_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
+v_subrev_f16_e64_dpp v5.l, v1.l, v2.l row_shl:15
+// GFX12: v_subrev_f16_e64_dpp v5.l, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
-v_subrev_f16_e64_dpp v5, v1, s2 row_shl:15
-// GFX12: v_subrev_f16_e64_dpp v5, v1, s2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x00,0x00,0x01,0x0f,0x01,0xff]
+v_subrev_f16_e64_dpp v5.l, v1.l, s2 row_shl:15
+// GFX12: v_subrev_f16_e64_dpp v5.l, v1.l, s2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x00,0x00,0x01,0x0f,0x01,0xff]
-v_subrev_f16_e64_dpp v5, v1, 2.0 row_shl:15
-// GFX12: v_subrev_f16_e64_dpp v5, v1, 2.0 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0xe8,0x01,0x00,0x01,0x0f,0x01,0xff]
+v_subrev_f16_e64_dpp v5.l, v1.l, 2.0 row_shl:15
+// GFX12: v_subrev_f16_e64_dpp v5.l, v1.l, 2.0 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0xe8,0x01,0x00,0x01,0x0f,0x01,0xff]
-v_subrev_f16_e64_dpp v5, v1, v2 row_shr:1
-// GFX12: v_subrev_f16_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
+v_subrev_f16_e64_dpp v5.l, v1.l, v2.l row_shr:1
+// GFX12: v_subrev_f16_e64_dpp v5.l, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
-v_subrev_f16_e64_dpp v5, v1, v2 row_shr:15
-// GFX12: v_subrev_f16_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
+v_subrev_f16_e64_dpp v5.l, v1.l, v2.l row_shr:15
+// GFX12: v_subrev_f16_e64_dpp v5.l, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
-v_subrev_f16_e64_dpp v5, v1, v2 row_ror:1
-// GFX12: v_subrev_f16_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
+v_subrev_f16_e64_dpp v5.l, v1.l, v2.l row_ror:1
+// GFX12: v_subrev_f16_e64_dpp v5.l, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
-v_subrev_f16_e64_dpp v5, v1, v2 row_ror:15
-// GFX12: v_subrev_f16_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
+v_subrev_f16_e64_dpp v5.l, v1.l, v2.l row_ror:15
+// GFX12: v_subrev_f16_e64_dpp v5.l, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
-v_subrev_f16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
-// GFX12: v_subrev_f16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+v_subrev_f16_e64_dpp v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: v_subrev_f16_e64_dpp v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
-v_subrev_f16_e64_dpp v5, |v1|, -v2 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
-// GFX12: v_subrev_f16_e64_dpp v5, |v1|, -v2 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x01,0x34,0xd5,0xfa,0x04,0x02,0x48,0x01,0x5f,0x01,0x01]
+v_subrev_f16_e64_dpp v5.l, |v1.l|, -v2.l mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: v_subrev_f16_e64_dpp v5.l, |v1.l|, -v2.l mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x01,0x34,0xd5,0xfa,0x04,0x02,0x48,0x01,0x5f,0x01,0x01]
-v_subrev_f16_e64_dpp v5, -v1, |v2| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
-// GFX12: v_subrev_f16_e64_dpp v5, -v1, |v2| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x05,0x02,0x34,0xd5,0xfa,0x04,0x02,0x30,0x01,0x60,0x09,0x13]
+v_subrev_f16_e64_dpp v5.l, -v1.l, |v2.l| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: v_subrev_f16_e64_dpp v5.l, -v1.l, |v2.l| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x05,0x02,0x34,0xd5,0xfa,0x04,0x02,0x30,0x01,0x60,0x09,0x13]
-v_subrev_f16_e64_dpp v255, -|v255|, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
-// GFX12: v_subrev_f16_e64_dpp v255, -|v255|, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xff,0x83,0x34,0xd5,0xfa,0xfe,0x03,0x78,0xff,0x6f,0x05,0x30]
+v_subrev_f16_e64_dpp v255.l, -|v255.l|, -|v255.l| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: v_subrev_f16_e64_dpp v255.l, -|v255.l|, -|v255.l| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xff,0x83,0x34,0xd5,0xfa,0xfe,0x03,0x78,0xff,0x6f,0x05,0x30]
+
+v_subrev_f16_e64_dpp v5.h, v1.h, v2.h row_share:0 row_mask:0xf bank_mask:0xf
+// GFX12: v_subrev_f16_e64_dpp v5.h, v1.h, v2.h op_sel:[1,1,1] row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x58,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
+
+v_subrev_f16_e64_dpp v5.l, |v1.h|, -v2.l mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+// GFX12: v_subrev_f16_e64_dpp v5.l, |v1.h|, -v2.l op_sel:[1,0,0] mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x09,0x34,0xd5,0xfa,0x04,0x02,0x48,0x01,0x5f,0x01,0x01]
+
+v_subrev_f16_e64_dpp v5.l, -v1.l, |v2.h| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+// GFX12: v_subrev_f16_e64_dpp v5.l, -v1.l, |v2.h| op_sel:[0,1,0] mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x05,0x12,0x34,0xd5,0xfa,0x04,0x02,0x30,0x01,0x60,0x09,0x13]
+
+v_subrev_f16_e64_dpp v255.h, -|v255.l|, -|v255.l| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+// GFX12: v_subrev_f16_e64_dpp v255.h, -|v255.l|, -|v255.l| op_sel:[0,0,1] clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xff,0xc3,0x34,0xd5,0xfa,0xfe,0x03,0x78,0xff,0x6f,0x05,0x30]
v_subrev_f32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0]
// GFX12: v_subrev_f32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x05,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2_dpp8.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2_dpp8.s
index 8d8f2f3b2a3faa..49233697e955cc 100644
--- a/llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2_dpp8.s
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2_dpp8.s
@@ -734,23 +734,35 @@ v_subrev_co_ci_u32_e64_dpp v5, ttmp[14:15], v1, v2, ttmp[14:15] dpp8:[7,6,5,4,3,
v_subrev_co_ci_u32_e64_dpp v255, null, v255, v255, null clamp dpp8:[0,0,0,0,0,0,0,0] fi:0
// GFX12: v_subrev_co_ci_u32_e64_dpp v255, null, v255, v255, null clamp dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xff,0xfc,0x22,0xd5,0xe9,0xfe,0xf3,0x01,0xff,0x00,0x00,0x00]
-v_subrev_f16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
-// GFX12: v_subrev_f16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x34,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+v_subrev_f16_e64_dpp v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_subrev_f16_e64_dpp v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x34,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
-v_subrev_f16_e64_dpp v5, v1, s2 dpp8:[7,6,5,4,3,2,1,0]
-// GFX12: v_subrev_f16_e64_dpp v5, v1, s2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x34,0xd5,0xe9,0x04,0x00,0x00,0x01,0x77,0x39,0x05]
+v_subrev_f16_e64_dpp v5.l, v1.l, s2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_subrev_f16_e64_dpp v5.l, v1.l, s2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x34,0xd5,0xe9,0x04,0x00,0x00,0x01,0x77,0x39,0x05]
-v_subrev_f16_e64_dpp v5, v1, 2.0 dpp8:[7,6,5,4,3,2,1,0]
-// GFX12: v_subrev_f16_e64_dpp v5, v1, 2.0 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x34,0xd5,0xe9,0xe8,0x01,0x00,0x01,0x77,0x39,0x05]
+v_subrev_f16_e64_dpp v5.l, v1.l, 2.0 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_subrev_f16_e64_dpp v5.l, v1.l, 2.0 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x34,0xd5,0xe9,0xe8,0x01,0x00,0x01,0x77,0x39,0x05]
-v_subrev_f16_e64_dpp v5, |v1|, -v2 mul:2 dpp8:[7,6,5,4,3,2,1,0]
-// GFX12: v_subrev_f16_e64_dpp v5, |v1|, -v2 mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x34,0xd5,0xe9,0x04,0x02,0x48,0x01,0x77,0x39,0x05]
+v_subrev_f16_e64_dpp v5.l, |v1.l|, -v2.l mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_subrev_f16_e64_dpp v5.l, |v1.l|, -v2.l mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x34,0xd5,0xe9,0x04,0x02,0x48,0x01,0x77,0x39,0x05]
-v_subrev_f16_e64_dpp v5, -v1, |v2| mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
-// GFX12: v_subrev_f16_e64_dpp v5, -v1, |v2| mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x05,0x02,0x34,0xd5,0xea,0x04,0x02,0x30,0x01,0x77,0x39,0x05]
+v_subrev_f16_e64_dpp v5.l, -v1.l, |v2.l| mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: v_subrev_f16_e64_dpp v5.l, -v1.l, |v2.l| mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x05,0x02,0x34,0xd5,0xea,0x04,0x02,0x30,0x01,0x77,0x39,0x05]
-v_subrev_f16_e64_dpp v255, -|v255|, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
-// GFX12: v_subrev_f16_e64_dpp v255, -|v255|, -|v255| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xff,0x83,0x34,0xd5,0xe9,0xfe,0x03,0x78,0xff,0x00,0x00,0x00]
+v_subrev_f16_e64_dpp v255.l, -|v255.l|, -|v255.l| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: v_subrev_f16_e64_dpp v255.l, -|v255.l|, -|v255.l| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xff,0x83,0x34,0xd5,0xe9,0xfe,0x03,0x78,0xff,0x00,0x00,0x00]
+
+v_subrev_f16_e64_dpp v5.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_subrev_f16_e64_dpp v5.h, v1.h, v2.h op_sel:[1,1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x58,0x34,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
+
+v_subrev_f16_e64_dpp v5.l, |v1.h|, -v2.l mul:2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: v_subrev_f16_e64_dpp v5.l, |v1.h|, -v2.l op_sel:[1,0,0] mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x09,0x34,0xd5,0xe9,0x04,0x02,0x48,0x01,0x77,0x39,0x05]
+
+v_subrev_f16_e64_dpp v5.l, -v1.l, |v2.h| mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12: v_subrev_f16_e64_dpp v5.l, -v1.l, |v2.h| op_sel:[0,1,0] mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x05,0x12,0x34,0xd5,0xea,0x04,0x02,0x30,0x01,0x77,0x39,0x05]
+
+v_subrev_f16_e64_dpp v255.h, -|v255.l|, -|v255.l| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
+// GFX12: v_subrev_f16_e64_dpp v255.h, -|v255.l|, -|v255.l| op_sel:[0,0,1] clamp div:2 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xff,0xc3,0x34,0xd5,0xe9,0xfe,0x03,0x78,0xff,0x00,0x00,0x00]
v_subrev_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
// GFX12: v_subrev_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x05,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05]
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