[llvm] [LiveVariables] Mark use as implicit-def if defined at instr (PR #119446)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 18 01:57:02 PST 2024
https://github.com/jofrn updated https://github.com/llvm/llvm-project/pull/119446
>From 6b852f9d05a1997167ed3b337559b3d43479b147 Mon Sep 17 00:00:00 2001
From: jofrn <jofernau at amd.com>
Date: Tue, 10 Dec 2024 11:53:21 -0800
Subject: [PATCH 1/5] [LiveVariables] Mark use as implicit-def if def is a
subregister
LiveVariables will mark instructions with their implicit subregister
uses. However, it will miss marking the subregister as an implicit-def
if its own definition is a subregister of it, i.e.
`$r3 = OP val, implicit-def $r0_r1_r2_r3, ..., implicit $r2_r3`,
which defines $sr3 on the same line it is used.
This change ensures such uses are marked as implicit-def, i.e.
`$r3 = OP val, implicit-def $r0_r1_r2_r3, ..., implicit-def $r2_r3`.
---
llvm/lib/CodeGen/LiveVariables.cpp | 17 +++++--
.../CodeGen/AMDGPU/implicitdef-subreg.mir | 46 +++++++++++++++++++
2 files changed, 60 insertions(+), 3 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/implicitdef-subreg.mir
diff --git a/llvm/lib/CodeGen/LiveVariables.cpp b/llvm/lib/CodeGen/LiveVariables.cpp
index f17d60dc22dda9..ec6c360561bd9c 100644
--- a/llvm/lib/CodeGen/LiveVariables.cpp
+++ b/llvm/lib/CodeGen/LiveVariables.cpp
@@ -277,11 +277,22 @@ void LiveVariables::HandlePhysRegUse(Register Reg, MachineInstr &MI) {
continue;
if (PartDefRegs.count(SubReg))
continue;
+
+ // Check if SubReg is defined at LastPartialDef.
+ bool IsDefinedHere = false;
+ for (int I = 0; I < LastPartialDef->getNumOperands(); ++I) {
+ const auto MO = LastPartialDef->getOperand(I);
+ if (!MO.isReg() || !MO.isDef())
+ continue;
+ if (TRI->isSubRegister(SubReg, MO.getReg())) {
+ IsDefinedHere = true;
+ break;
+ }
+ }
// This part of Reg was defined before the last partial def. It's killed
// here.
- LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg,
- false/*IsDef*/,
- true/*IsImp*/));
+ LastPartialDef->addOperand(
+ MachineOperand::CreateReg(SubReg, IsDefinedHere, true /*IsImp*/));
PhysRegDef[SubReg] = LastPartialDef;
for (MCPhysReg SS : TRI->subregs(SubReg))
Processed.insert(SS);
diff --git a/llvm/test/CodeGen/AMDGPU/implicitdef-subreg.mir b/llvm/test/CodeGen/AMDGPU/implicitdef-subreg.mir
new file mode 100644
index 00000000000000..4f5bc49dabfdae
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/implicitdef-subreg.mir
@@ -0,0 +1,46 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=amdgcn --run-pass=livevars -o - %s | FileCheck %s
+---
+name: sgpr_copy
+tracksRegLiveness: true
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: sgpr_copy
+ ; CHECK: %sval:sreg_32 = S_MOV_B32 0
+ ; CHECK-NEXT: $sgpr0 = COPY %sval
+ ; CHECK-NEXT: $sgpr1 = COPY %sval
+ ; CHECK-NEXT: $sgpr2 = COPY %sval
+ ; CHECK-NEXT: $sgpr3 = COPY killed %sval, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr0_sgpr1, implicit $sgpr0_sgpr1_sgpr2, implicit-def $sgpr2_sgpr3
+ ; CHECK-NEXT: dead $sgpr30_sgpr31 = COPY killed $sgpr0_sgpr1_sgpr2_sgpr3
+
+ %sval:sreg_32 = S_MOV_B32 0
+
+ $sgpr0 = COPY %sval
+ $sgpr1 = COPY %sval
+ $sgpr2 = COPY %sval
+ $sgpr3 = COPY %sval
+ $sgpr30_sgpr31 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
+
+...
+---
+name: vgpr_copy
+tracksRegLiveness: true
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: vgpr_copy
+ ; CHECK: %vval:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: $vgpr0 = COPY %vval
+ ; CHECK-NEXT: $vgpr1 = COPY %vval
+ ; CHECK-NEXT: $vgpr2 = COPY %vval
+ ; CHECK-NEXT: $vgpr3 = COPY killed %vval, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr0_vgpr1, implicit $vgpr0_vgpr1_vgpr2, implicit-def $vgpr1_vgpr2_vgpr3
+ ; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vgpr_32 = COPY killed $vgpr0_vgpr1_vgpr2_vgpr3
+
+ %vval:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+
+ $vgpr0 = COPY %vval
+ $vgpr1 = COPY %vval
+ $vgpr2 = COPY %vval
+ $vgpr3 = COPY %vval
+ %0:vgpr_32 = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+
+...
>From 0208eb91b91c5b211d661853cd3a12b6b88e0701 Mon Sep 17 00:00:00 2001
From: jofrn <jofernau at amd.com>
Date: Wed, 11 Dec 2024 01:24:12 -0800
Subject: [PATCH 2/5] Rewrite loop to be modifiesRegister
This also causes superregisters to be marked as implicit-def.
---
llvm/lib/CodeGen/LiveVariables.cpp | 11 +----------
llvm/test/CodeGen/AArch64/ldrpre-ldr-merge.mir | 2 +-
llvm/test/CodeGen/AMDGPU/implicitdef-subreg.mir | 8 ++++----
3 files changed, 6 insertions(+), 15 deletions(-)
diff --git a/llvm/lib/CodeGen/LiveVariables.cpp b/llvm/lib/CodeGen/LiveVariables.cpp
index ec6c360561bd9c..39d26580308983 100644
--- a/llvm/lib/CodeGen/LiveVariables.cpp
+++ b/llvm/lib/CodeGen/LiveVariables.cpp
@@ -279,16 +279,7 @@ void LiveVariables::HandlePhysRegUse(Register Reg, MachineInstr &MI) {
continue;
// Check if SubReg is defined at LastPartialDef.
- bool IsDefinedHere = false;
- for (int I = 0; I < LastPartialDef->getNumOperands(); ++I) {
- const auto MO = LastPartialDef->getOperand(I);
- if (!MO.isReg() || !MO.isDef())
- continue;
- if (TRI->isSubRegister(SubReg, MO.getReg())) {
- IsDefinedHere = true;
- break;
- }
- }
+ bool IsDefinedHere = LastPartialDef->modifiesRegister(SubReg, TRI);
// This part of Reg was defined before the last partial def. It's killed
// here.
LastPartialDef->addOperand(
diff --git a/llvm/test/CodeGen/AArch64/ldrpre-ldr-merge.mir b/llvm/test/CodeGen/AArch64/ldrpre-ldr-merge.mir
index a10d7588cb4429..c2fba541bdd1e4 100644
--- a/llvm/test/CodeGen/AArch64/ldrpre-ldr-merge.mir
+++ b/llvm/test/CodeGen/AArch64/ldrpre-ldr-merge.mir
@@ -756,7 +756,7 @@ body: |
; CHECK: liveins: $x0, $x1, $x2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: early-clobber renamable $x1, renamable $x0 = LDRSWpre renamable $x1, 40, implicit $w1, implicit $w1_hi :: (load (s32))
- ; CHECK-NEXT: renamable $w2 = LDRWui renamable $x1, 1, implicit-def $x2, implicit $w2_hi :: (load (s32))
+ ; CHECK-NEXT: renamable $w2 = LDRWui renamable $x1, 1, implicit-def $x2, implicit-def $w2_hi :: (load (s32))
; CHECK-NEXT: STPXi renamable $x0, renamable $x2, renamable $x1, 0 :: (store (s64))
; CHECK-NEXT: RET undef $lr
early-clobber renamable $x1, renamable $x0 = LDRSWpre killed renamable $x1, 40 :: (load (s32))
diff --git a/llvm/test/CodeGen/AMDGPU/implicitdef-subreg.mir b/llvm/test/CodeGen/AMDGPU/implicitdef-subreg.mir
index 4f5bc49dabfdae..dd6352586f2e57 100644
--- a/llvm/test/CodeGen/AMDGPU/implicitdef-subreg.mir
+++ b/llvm/test/CodeGen/AMDGPU/implicitdef-subreg.mir
@@ -5,14 +5,14 @@ name: sgpr_copy
tracksRegLiveness: true
body: |
bb.0:
+
; CHECK-LABEL: name: sgpr_copy
; CHECK: %sval:sreg_32 = S_MOV_B32 0
; CHECK-NEXT: $sgpr0 = COPY %sval
; CHECK-NEXT: $sgpr1 = COPY %sval
; CHECK-NEXT: $sgpr2 = COPY %sval
- ; CHECK-NEXT: $sgpr3 = COPY killed %sval, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr0_sgpr1, implicit $sgpr0_sgpr1_sgpr2, implicit-def $sgpr2_sgpr3
+ ; CHECK-NEXT: $sgpr3 = COPY killed %sval, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3, implicit-def $sgpr0, implicit-def $sgpr1, implicit-def $sgpr2, implicit-def $sgpr0_sgpr1, implicit-def $sgpr0_sgpr1_sgpr2, implicit-def $sgpr2_sgpr3
; CHECK-NEXT: dead $sgpr30_sgpr31 = COPY killed $sgpr0_sgpr1_sgpr2_sgpr3
-
%sval:sreg_32 = S_MOV_B32 0
$sgpr0 = COPY %sval
@@ -27,14 +27,14 @@ name: vgpr_copy
tracksRegLiveness: true
body: |
bb.0:
+
; CHECK-LABEL: name: vgpr_copy
; CHECK: %vval:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; CHECK-NEXT: $vgpr0 = COPY %vval
; CHECK-NEXT: $vgpr1 = COPY %vval
; CHECK-NEXT: $vgpr2 = COPY %vval
- ; CHECK-NEXT: $vgpr3 = COPY killed %vval, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr0_vgpr1, implicit $vgpr0_vgpr1_vgpr2, implicit-def $vgpr1_vgpr2_vgpr3
+ ; CHECK-NEXT: $vgpr3 = COPY killed %vval, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2, implicit-def $vgpr0_vgpr1, implicit-def $vgpr0_vgpr1_vgpr2, implicit-def $vgpr1_vgpr2_vgpr3
; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vgpr_32 = COPY killed $vgpr0_vgpr1_vgpr2_vgpr3
-
%vval:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
$vgpr0 = COPY %vval
>From e0cd95a70d8d348e2364fee4479f953dcb21f775 Mon Sep 17 00:00:00 2001
From: jofernau <Joe.Fernau at amd.com>
Date: Wed, 11 Dec 2024 02:52:19 -0800
Subject: [PATCH 3/5] Add ll test
---
.../test/CodeGen/AMDGPU/fncall-implicitdef.ll | 28 +++++++++++++++++++
1 file changed, 28 insertions(+)
create mode 100644 llvm/test/CodeGen/AMDGPU/fncall-implicitdef.ll
diff --git a/llvm/test/CodeGen/AMDGPU/fncall-implicitdef.ll b/llvm/test/CodeGen/AMDGPU/fncall-implicitdef.ll
new file mode 100644
index 00000000000000..9c053219c0b316
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/fncall-implicitdef.ll
@@ -0,0 +1,28 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -O1 %s -o - | FileCheck %s
+
+define amdgpu_ps <4 x float> @caller(ptr %1) {
+; CHECK-LABEL: caller:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: flat_load_dword v1, v[0:1]
+; CHECK-NEXT: s_getpc_b64 s[0:1]
+; CHECK-NEXT: s_add_u32 s0, s0, fn at gotpcrel32@lo+4
+; CHECK-NEXT: s_addc_u32 s1, s1, fn at gotpcrel32@hi+12
+; CHECK-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x0
+; CHECK-NEXT: s_mov_b32 s0, 0
+; CHECK-NEXT: s_mov_b32 s1, 0
+; CHECK-NEXT: s_mov_b32 s2, 0
+; CHECK-NEXT: s_mov_b64 s[8:9], 36
+; CHECK-NEXT: v_mov_b32_e32 v0, 0
+; CHECK-NEXT: s_mov_b32 s3, 0
+; CHECK-NEXT: v_mov_b32_e32 v2, 0
+; CHECK-NEXT: s_mov_b32 s32, 0
+; CHECK-NEXT: s_waitcnt lgkmcnt(0)
+; CHECK-NEXT: s_swappc_b64 s[30:31], s[4:5]
+; CHECK-NEXT: ; return to shader part epilog
+ %L = load i32, ptr %1, align 4
+ %R = call <4 x float> @fn(<4 x i32> zeroinitializer, i32 0, i32 %L, i32 0)
+ ret <4 x float> %R
+}
+
+declare <4 x float> @fn(<4 x i32> inreg, i32, i32, i32)
>From 1fa40b79512173fcff5d27a075e2c75dd045d064 Mon Sep 17 00:00:00 2001
From: jofernau <Joe.Fernau at amd.com>
Date: Thu, 12 Dec 2024 07:52:53 -0800
Subject: [PATCH 4/5] Rename test, use named value & declare hidden
---
llvm/test/CodeGen/AMDGPU/fncall-implicitdef.ll | 14 ++++++--------
...icitdef-subreg.mir => livevars-implicitdef.mir} | 0
2 files changed, 6 insertions(+), 8 deletions(-)
rename llvm/test/CodeGen/AMDGPU/{implicitdef-subreg.mir => livevars-implicitdef.mir} (100%)
diff --git a/llvm/test/CodeGen/AMDGPU/fncall-implicitdef.ll b/llvm/test/CodeGen/AMDGPU/fncall-implicitdef.ll
index 9c053219c0b316..551ae4dd3faae6 100644
--- a/llvm/test/CodeGen/AMDGPU/fncall-implicitdef.ll
+++ b/llvm/test/CodeGen/AMDGPU/fncall-implicitdef.ll
@@ -1,14 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -O1 %s -o - | FileCheck %s
-define amdgpu_ps <4 x float> @caller(ptr %1) {
+define amdgpu_ps <4 x float> @caller(ptr %ptr) {
; CHECK-LABEL: caller:
; CHECK: ; %bb.0:
; CHECK-NEXT: flat_load_dword v1, v[0:1]
-; CHECK-NEXT: s_getpc_b64 s[0:1]
-; CHECK-NEXT: s_add_u32 s0, s0, fn at gotpcrel32@lo+4
-; CHECK-NEXT: s_addc_u32 s1, s1, fn at gotpcrel32@hi+12
-; CHECK-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x0
; CHECK-NEXT: s_mov_b32 s0, 0
; CHECK-NEXT: s_mov_b32 s1, 0
; CHECK-NEXT: s_mov_b32 s2, 0
@@ -17,12 +13,14 @@ define amdgpu_ps <4 x float> @caller(ptr %1) {
; CHECK-NEXT: s_mov_b32 s3, 0
; CHECK-NEXT: v_mov_b32_e32 v2, 0
; CHECK-NEXT: s_mov_b32 s32, 0
-; CHECK-NEXT: s_waitcnt lgkmcnt(0)
+; CHECK-NEXT: s_getpc_b64 s[4:5]
+; CHECK-NEXT: s_add_u32 s4, s4, fn at rel32@lo+4
+; CHECK-NEXT: s_addc_u32 s5, s5, fn at rel32@hi+12
; CHECK-NEXT: s_swappc_b64 s[30:31], s[4:5]
; CHECK-NEXT: ; return to shader part epilog
- %L = load i32, ptr %1, align 4
+ %L = load i32, ptr %ptr, align 4
%R = call <4 x float> @fn(<4 x i32> zeroinitializer, i32 0, i32 %L, i32 0)
ret <4 x float> %R
}
-declare <4 x float> @fn(<4 x i32> inreg, i32, i32, i32)
+declare hidden <4 x float> @fn(<4 x i32> inreg, i32, i32, i32)
diff --git a/llvm/test/CodeGen/AMDGPU/implicitdef-subreg.mir b/llvm/test/CodeGen/AMDGPU/livevars-implicitdef.mir
similarity index 100%
rename from llvm/test/CodeGen/AMDGPU/implicitdef-subreg.mir
rename to llvm/test/CodeGen/AMDGPU/livevars-implicitdef.mir
>From 86d785fd06fafb9cb0c333a1e1d0bd92f7ec46a4 Mon Sep 17 00:00:00 2001
From: jofernau <Joe.Fernau at amd.com>
Date: Wed, 18 Dec 2024 01:47:18 -0800
Subject: [PATCH 5/5] Delete FindLastPartialDef part of HandlePhysRegUse
---
llvm/include/llvm/CodeGen/LiveVariables.h | 6 --
llvm/lib/CodeGen/LiveVariables.cpp | 72 +------------------
.../test/CodeGen/AArch64/ldrpre-ldr-merge.mir | 2 +-
.../test/CodeGen/AMDGPU/fncall-implicitdef.ll | 4 +-
.../CodeGen/AMDGPU/livevars-implicitdef.mir | 4 +-
5 files changed, 6 insertions(+), 82 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/LiveVariables.h b/llvm/include/llvm/CodeGen/LiveVariables.h
index 89d1b5edf3fa63..93888dbeb17220 100644
--- a/llvm/include/llvm/CodeGen/LiveVariables.h
+++ b/llvm/include/llvm/CodeGen/LiveVariables.h
@@ -163,12 +163,6 @@ class LiveVariables {
/// the specified register.
MachineInstr *FindLastRefOrPartRef(Register Reg);
- /// FindLastPartialDef - Return the last partial def of the specified
- /// register. Also returns the sub-registers that're defined by the
- /// instruction.
- MachineInstr *FindLastPartialDef(Register Reg,
- SmallSet<unsigned, 4> &PartDefRegs);
-
/// analyzePHINodes - Gather information about the PHI nodes in here. In
/// particular, we want to map the variable information of a virtual
/// register which is used in a PHI node. We map that to the BB the vreg
diff --git a/llvm/lib/CodeGen/LiveVariables.cpp b/llvm/lib/CodeGen/LiveVariables.cpp
index 39d26580308983..49684e78a24733 100644
--- a/llvm/lib/CodeGen/LiveVariables.cpp
+++ b/llvm/lib/CodeGen/LiveVariables.cpp
@@ -213,83 +213,13 @@ void LiveVariables::HandleVirtRegDef(Register Reg, MachineInstr &MI) {
VRInfo.Kills.push_back(&MI);
}
-/// FindLastPartialDef - Return the last partial def of the specified register.
-/// Also returns the sub-registers that're defined by the instruction.
-MachineInstr *
-LiveVariables::FindLastPartialDef(Register Reg,
- SmallSet<unsigned, 4> &PartDefRegs) {
- unsigned LastDefReg = 0;
- unsigned LastDefDist = 0;
- MachineInstr *LastDef = nullptr;
- for (MCPhysReg SubReg : TRI->subregs(Reg)) {
- MachineInstr *Def = PhysRegDef[SubReg];
- if (!Def)
- continue;
- unsigned Dist = DistanceMap[Def];
- if (Dist > LastDefDist) {
- LastDefReg = SubReg;
- LastDef = Def;
- LastDefDist = Dist;
- }
- }
-
- if (!LastDef)
- return nullptr;
-
- PartDefRegs.insert(LastDefReg);
- for (MachineOperand &MO : LastDef->all_defs()) {
- if (MO.getReg() == 0)
- continue;
- Register DefReg = MO.getReg();
- if (TRI->isSubRegister(Reg, DefReg)) {
- for (MCPhysReg SubReg : TRI->subregs_inclusive(DefReg))
- PartDefRegs.insert(SubReg);
- }
- }
- return LastDef;
-}
-
/// HandlePhysRegUse - Turn previous partial def's into read/mod/writes. Add
/// implicit defs to a machine instruction if there was an earlier def of its
/// super-register.
void LiveVariables::HandlePhysRegUse(Register Reg, MachineInstr &MI) {
MachineInstr *LastDef = PhysRegDef[Reg];
// If there was a previous use or a "full" def all is well.
- if (!LastDef && !PhysRegUse[Reg]) {
- // Otherwise, the last sub-register def implicitly defines this register.
- // e.g.
- // AH =
- // AL = ... implicit-def EAX, implicit killed AH
- // = AH
- // ...
- // = EAX
- // All of the sub-registers must have been defined before the use of Reg!
- SmallSet<unsigned, 4> PartDefRegs;
- MachineInstr *LastPartialDef = FindLastPartialDef(Reg, PartDefRegs);
- // If LastPartialDef is NULL, it must be using a livein register.
- if (LastPartialDef) {
- LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/,
- true/*IsImp*/));
- PhysRegDef[Reg] = LastPartialDef;
- SmallSet<unsigned, 8> Processed;
- for (MCPhysReg SubReg : TRI->subregs(Reg)) {
- if (Processed.count(SubReg))
- continue;
- if (PartDefRegs.count(SubReg))
- continue;
-
- // Check if SubReg is defined at LastPartialDef.
- bool IsDefinedHere = LastPartialDef->modifiesRegister(SubReg, TRI);
- // This part of Reg was defined before the last partial def. It's killed
- // here.
- LastPartialDef->addOperand(
- MachineOperand::CreateReg(SubReg, IsDefinedHere, true /*IsImp*/));
- PhysRegDef[SubReg] = LastPartialDef;
- for (MCPhysReg SS : TRI->subregs(SubReg))
- Processed.insert(SS);
- }
- }
- } else if (LastDef && !PhysRegUse[Reg] &&
+ if (LastDef && !PhysRegUse[Reg] &&
!LastDef->findRegisterDefOperand(Reg, /*TRI=*/nullptr))
// Last def defines the super register, add an implicit def of reg.
LastDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/,
diff --git a/llvm/test/CodeGen/AArch64/ldrpre-ldr-merge.mir b/llvm/test/CodeGen/AArch64/ldrpre-ldr-merge.mir
index c2fba541bdd1e4..83fa969678b3a7 100644
--- a/llvm/test/CodeGen/AArch64/ldrpre-ldr-merge.mir
+++ b/llvm/test/CodeGen/AArch64/ldrpre-ldr-merge.mir
@@ -756,7 +756,7 @@ body: |
; CHECK: liveins: $x0, $x1, $x2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: early-clobber renamable $x1, renamable $x0 = LDRSWpre renamable $x1, 40, implicit $w1, implicit $w1_hi :: (load (s32))
- ; CHECK-NEXT: renamable $w2 = LDRWui renamable $x1, 1, implicit-def $x2, implicit-def $w2_hi :: (load (s32))
+ ; CHECK-NEXT: renamable $w2 = LDRWui renamable $x1, 1 :: (load (s32))
; CHECK-NEXT: STPXi renamable $x0, renamable $x2, renamable $x1, 0 :: (store (s64))
; CHECK-NEXT: RET undef $lr
early-clobber renamable $x1, renamable $x0 = LDRSWpre killed renamable $x1, 40 :: (load (s32))
diff --git a/llvm/test/CodeGen/AMDGPU/fncall-implicitdef.ll b/llvm/test/CodeGen/AMDGPU/fncall-implicitdef.ll
index 551ae4dd3faae6..0bc796d264e6ca 100644
--- a/llvm/test/CodeGen/AMDGPU/fncall-implicitdef.ll
+++ b/llvm/test/CodeGen/AMDGPU/fncall-implicitdef.ll
@@ -5,12 +5,12 @@ define amdgpu_ps <4 x float> @caller(ptr %ptr) {
; CHECK-LABEL: caller:
; CHECK: ; %bb.0:
; CHECK-NEXT: flat_load_dword v1, v[0:1]
+; CHECK-NEXT: s_mov_b64 s[8:9], 36
; CHECK-NEXT: s_mov_b32 s0, 0
; CHECK-NEXT: s_mov_b32 s1, 0
; CHECK-NEXT: s_mov_b32 s2, 0
-; CHECK-NEXT: s_mov_b64 s[8:9], 36
-; CHECK-NEXT: v_mov_b32_e32 v0, 0
; CHECK-NEXT: s_mov_b32 s3, 0
+; CHECK-NEXT: v_mov_b32_e32 v0, 0
; CHECK-NEXT: v_mov_b32_e32 v2, 0
; CHECK-NEXT: s_mov_b32 s32, 0
; CHECK-NEXT: s_getpc_b64 s[4:5]
diff --git a/llvm/test/CodeGen/AMDGPU/livevars-implicitdef.mir b/llvm/test/CodeGen/AMDGPU/livevars-implicitdef.mir
index dd6352586f2e57..e6f05cad1b09c5 100644
--- a/llvm/test/CodeGen/AMDGPU/livevars-implicitdef.mir
+++ b/llvm/test/CodeGen/AMDGPU/livevars-implicitdef.mir
@@ -11,7 +11,7 @@ body: |
; CHECK-NEXT: $sgpr0 = COPY %sval
; CHECK-NEXT: $sgpr1 = COPY %sval
; CHECK-NEXT: $sgpr2 = COPY %sval
- ; CHECK-NEXT: $sgpr3 = COPY killed %sval, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3, implicit-def $sgpr0, implicit-def $sgpr1, implicit-def $sgpr2, implicit-def $sgpr0_sgpr1, implicit-def $sgpr0_sgpr1_sgpr2, implicit-def $sgpr2_sgpr3
+ ; CHECK-NEXT: $sgpr3 = COPY killed %sval
; CHECK-NEXT: dead $sgpr30_sgpr31 = COPY killed $sgpr0_sgpr1_sgpr2_sgpr3
%sval:sreg_32 = S_MOV_B32 0
@@ -33,7 +33,7 @@ body: |
; CHECK-NEXT: $vgpr0 = COPY %vval
; CHECK-NEXT: $vgpr1 = COPY %vval
; CHECK-NEXT: $vgpr2 = COPY %vval
- ; CHECK-NEXT: $vgpr3 = COPY killed %vval, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2, implicit-def $vgpr0_vgpr1, implicit-def $vgpr0_vgpr1_vgpr2, implicit-def $vgpr1_vgpr2_vgpr3
+ ; CHECK-NEXT: $vgpr3 = COPY killed %vval
; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vgpr_32 = COPY killed $vgpr0_vgpr1_vgpr2_vgpr3
%vval:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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