[llvm] Port `NVPTXTargetLowering::LowerCONCAT_VECTORS` to SelectionDAG (PR #120030)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 17 22:13:22 PST 2024
================
@@ -1517,10 +1518,27 @@ SDValue SelectionDAGLegalize::ExpandInsertToVectorThroughStack(SDValue Op) {
BaseVecAlignment);
}
+SDValue SelectionDAGLegalize::ExpandConcatVectors(SDNode *Node) {
+ assert(Node->getOpcode() == ISD::CONCAT_VECTORS && "Unexpected opcode!");
+ SDLoc DL(Node);
+ SmallVector<SDValue, 16> Ops;
+ unsigned NumOperands = Node->getNumOperands();
+ MVT VectorIdxType = TLI.getVectorIdxTy(DAG.getDataLayout());
+ for (unsigned I = 0; I < NumOperands; ++I) {
+ SDValue SubOp = Node->getOperand(I);
+ EVT VectorValueType = SubOp.getValueType();
+ EVT ElementValueType = VectorValueType.getVectorElementType();
+ unsigned NumSubElem = VectorValueType.getVectorNumElements();
+ for (unsigned Idx = 0; Idx < NumSubElem; ++Idx) {
+ Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElementValueType,
+ SubOp, DAG.getConstant(Idx, DL, VectorIdxType)));
----------------
arsenm wrote:
EXTRACT_VECTOR_ELT has the weird property of supporting some implicit casts from the source vector to the result element, you'll probably need to adjust the input.
But yes this is a forever DAG design flaw. GlobalISel does not have this problem
https://github.com/llvm/llvm-project/pull/120030
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