[llvm] [RISCV][VLOPT] Add getOperandInfo for saturating signed multiply (PR #120351)

[Michael Maitland via llvm-commits]

https://github.com/michaelmaitland created https://github.com/llvm/llvm-project/pull/120351

These instructions are covered by the existing tests. We do not add them to isSupportedInstr because they have a tied def which means they will never get to that point in isCandidate.

>From 92a73e85fb69ebba3b7ff538261f3adaf48fa7b0 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Tue, 17 Dec 2024 19:33:23 -0800
Subject: [PATCH] [RISCV][VLOPT] Add getOperandInfo for saturating signed
 multiply

These instructions are covered by the existing tests. We do not add them to
isSupportedInstr because they have a tied def which means they will never
get to that point in isCandidate.
---
 llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
index e8719d02cfa0aa..9ee6ec2498d309 100644
--- a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
@@ -378,6 +378,11 @@ static OperandInfo getOperandInfo(const MachineOperand &MO,
   case RISCV::VASUBU_VX:
   case RISCV::VASUB_VV:
   case RISCV::VASUB_VX:
+  // Vector Single-Width Fractional Multiply with Rounding and Saturation
+  // EEW=SEW. EMUL=LMUL. The instruction produces 2*SEW product internally but
+  // saturates to fit into SEW bits.
+  case RISCV::VSMUL_VV:
+  case RISCV::VSMUL_VX:
   // Vector Single-Width Scaling Shift Instructions
   // EEW=SEW. EMUL=LMUL.
   case RISCV::VSSRL_VI: