[llvm] [RISCV] Add some additional notes about mask pseudo instructions to RISCVVectorExtension.rst. NFC (PR #120337)

[Craig Topper via llvm-commits]

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/120337

None

>From 6630321aec5d1077804159e3eccc993b772ea4d2 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Tue, 17 Dec 2024 16:03:24 -0800
Subject: [PATCH] [RISCV] Add some additional notes about mask pseudo
 instructions to RISCVVectorExtension.rst. NFC

---
 llvm/docs/RISCV/RISCVVectorExtension.rst | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/llvm/docs/RISCV/RISCVVectorExtension.rst b/llvm/docs/RISCV/RISCVVectorExtension.rst
index 39836a4b1ab9c0..a3adb8bb0a7366 100644
--- a/llvm/docs/RISCV/RISCVVectorExtension.rst
+++ b/llvm/docs/RISCV/RISCVVectorExtension.rst
@@ -233,6 +233,9 @@ For scalable vectors that should use VLMAX, the AVL is set to a sentinel value o
 
 There are patterns for target agnostic SelectionDAG nodes in ``RISCVInstrInfoVSDPatterns.td``, VL nodes in ``RISCVInstrInfoVVLPatterns.td`` and RVV intrinsics in ``RISCVInstrInfoVPseudos.td``.
 
+Instructions that operate only on masks like VMAND or VMSBF uses pseudo instructions suffixed with B1, B2, B4, B8, B16, B32, or B64 where the number is SEW/LMUL representing
+the ratio between SEW and LMUL needed in vtype. These instructions always operate as if EEW=1 and always use a value of 0 as their SEW operand.
+
 Mask patterns
 -------------