[llvm] [RISCV][VLOPT] Add vector indexed loads and stores to getOperandInfo (PR #119748)

[Craig Topper via llvm-commits]

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@@ -543,6 +543,122 @@ body: |
     PseudoVSSE8_V_MF2 %x, $noreg, $noreg, 1, 3 /* e8 */
 ...
 ---
+name: vsuxeiN_v_data
+body: |
+  bb.0:
+    ; CHECK-LABEL: name: vsuxeiN_v_data
+    ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
+    ; CHECK-NEXT: PseudoVSUXEI8_V_M1_M1 %x, $noreg, $noreg, 1, 3 /* e8 */
+    %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
+    PseudoVSUXEI8_V_M1_M1 %x, $noreg, $noreg, 1, 3 /* e8 */
+...
+---
+name: vsuxeiN_v_data_incompatible_eew
+body: |
+  bb.0:
+    ; CHECK-LABEL: name: vsuxeiN_v_data_incompatible_eew
+    ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */
+    ; CHECK-NEXT: PseudoVSUXEI8_V_M1_M1 %x, $noreg, $noreg, 1, 3 /* e8 */
+    %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0
+    PseudoVSUXEI8_V_M1_M1 %x, $noreg, $noreg, 1, 3 /* e8 */
+...
+---
+name: vsuxeiN_v_data_incompatible_emul
+body: |
+  bb.0:
+    ; CHECK-LABEL: name: vsuxeiN_v_data_incompatible_emul
+    ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
+    ; CHECK-NEXT: PseudoVSUXEI8_V_MF2_MF2 %x, $noreg, $noreg, 1, 3 /* e8 */
+    %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
+    PseudoVSUXEI8_V_MF2_MF2 %x, $noreg, $noreg, 1, 3 /* e8 */
+...
+# VSUX requires that the data register be a virtual register, so give it one
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topperc wrote:

Where does this requirement come from?

https://github.com/llvm/llvm-project/pull/119748