[llvm] e8ce6c4 - [RISCV] Fix typo in CV_SH_rr_inc pattern (#120246)

[via llvm-commits]

Author: Philipp van Kempen
Date: 2024-12-17T12:20:17-08:00
New Revision: e8ce6c4e69745b1b2cd6f7479c48fbae44622cb3

URL: https://github.com/llvm/llvm-project/commit/e8ce6c4e69745b1b2cd6f7479c48fbae44622cb3
DIFF: https://github.com/llvm/llvm-project/commit/e8ce6c4e69745b1b2cd6f7479c48fbae44622cb3.diff

LOG: [RISCV] Fix typo in CV_SH_rr_inc pattern (#120246)

This typo in
https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td#L701:L701
caused a compiler crash in 'RISC-V Assembly Printer' because
CV_SH_ri_inc was selected, leading to `getImmOpValue` being called for a
register operand.

This bug did not affect the Assembler output and therefore does not
trigger any existing unit tests, but is visible by examining the final
MIR function.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
index 4478e246111080..b98934d8c63964 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
@@ -698,7 +698,7 @@ let Predicates = [HasVendorXCVmem, IsRV32], AddedComplexity = 1 in {
   def : CVStriPat<post_store, CV_SW_ri_inc>;
 
   def : CVStrriPat<post_truncsti8, CV_SB_rr_inc>;
-  def : CVStrriPat<post_truncsti16, CV_SH_ri_inc>;
+  def : CVStrriPat<post_truncsti16, CV_SH_rr_inc>;
   def : CVStrriPat<post_store, CV_SW_rr_inc>;
 
   def : CVStrrPat<truncstorei8, CV_SB_rr>;