[llvm] [RISC-V] Base scheduling model for tt-ascalon-d8 (PR #120160)

[Petr Penzin via llvm-commits]

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@@ -0,0 +1,333 @@
+//=- RISCVSchedTTAscalonD8.td - TT Ascalon D8 Sched Defs -----*- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+
+def TTAscalonD8Model : SchedMachineModel {
+  let IssueWidth        =   8; // 8-way decode and dispatch
+  let MicroOpBufferSize = 256; // 256 micro-op re-order buffer
+  let LoadLatency       =   4; // Optimistic load latency
+  let MispredictPenalty =  14; // Fetch + Decode/Rename/Dispatch + Branch
+
+  // Enable partial & runtime unrolling.
+  let LoopMicroOpBufferSize = 16;
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ppenzin wrote:

Good point, addressed.

https://github.com/llvm/llvm-project/pull/120160