[llvm] [RISCV] Select and/or/xor with certain constants to Zbb ANDN/ORN/XNOR (PR #120221)

[Craig Topper via llvm-commits]

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@@ -481,6 +481,25 @@ def : Pat<(XLenVT (or  GPR:$rs1, (not GPR:$rs2))), (ORN  GPR:$rs1, GPR:$rs2)>;
 def : Pat<(XLenVT (xor GPR:$rs1, (not GPR:$rs2))), (XNOR GPR:$rs1, GPR:$rs2)>;
 } // Predicates = [HasStdExtZbbOrZbkb]
 
+// A 32-bit signed immediate with all 12 low bits set, but not -1
+def simm32fff : ImmLeaf<XLenVT, [{
+  return isInt<32>(Imm) && (Imm & 0xfff) == 0xfff && Imm != -1;}]>;
+
+def NotImm : SDNodeXForm<imm, [{
+  return CurDAG->getTargetConstant(~N->getSExtValue(), SDLoc(N),
+                                   N->getValueType(0));
+}]>;
+
+class PatGprSimm32fff<SDPatternOperator OpNode, RVInst Inst>
+    : Pat<(XLenVT (OpNode (vt GPR:$rs1), simm32fff:$imm)),
+          (Inst GPR:$rs1, (NotImm simm32fff:$imm))>;
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topperc wrote:

We need to explicitly create an LUI for the immediate here. And we need to put the immediate into LUI format which requires shifting right by 12 and masking to 20 bits.

https://github.com/llvm/llvm-project/pull/120221