[llvm] [RISCV] Check for register where immediate should be in RISCVInstrInfo::verifyInstruction. (PR #120286)

[Craig Topper via llvm-commits]

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/120286

The generic verifier will do this if the operand type is OPERAND_IMMEDIATE, but we use our own custom operand types. Immediate operands are still allowed to be globals, constant pools, blockaddress, etc. so we can't check !isImm().

Fix the same typo as #120246 which is now detected by this.

CC: @PhilippvK 

>From 919bbfb5a7e6b9453a634562bb66759b1c8e7fce Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Tue, 17 Dec 2024 10:44:33 -0800
Subject: [PATCH] [RISCV] Check for register where immediate should be in
 RISCVInstrInfo::verifyInstruction.

The generic verifier will do this if the operand type is
OPERAND_IMMEDIATE, but we use our own custom operand types.
Immediate operands are still allowed to be globals, constant pools,
blockaddress, etc. so we can't check !isImm().

Fix the same typo as #120246 which is now detected by this.
---
 llvm/lib/Target/RISCV/RISCVInstrInfo.cpp   | 4 ++++
 llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td | 2 +-
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 0944e7d461f8e5..7e0063589b6f4c 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -2451,6 +2451,10 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
     if (OpType >= RISCVOp::OPERAND_FIRST_RISCV_IMM &&
         OpType <= RISCVOp::OPERAND_LAST_RISCV_IMM) {
       const MachineOperand &MO = MI.getOperand(Index);
+      if (MO.isReg()) {
+        ErrInfo = "Expected a non-register operand.";
+        return false;
+      }
       if (MO.isImm()) {
         int64_t Imm = MO.getImm();
         bool Ok;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
index 4478e246111080..b98934d8c63964 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
@@ -698,7 +698,7 @@ let Predicates = [HasVendorXCVmem, IsRV32], AddedComplexity = 1 in {
   def : CVStriPat<post_store, CV_SW_ri_inc>;
 
   def : CVStrriPat<post_truncsti8, CV_SB_rr_inc>;
-  def : CVStrriPat<post_truncsti16, CV_SH_ri_inc>;
+  def : CVStrriPat<post_truncsti16, CV_SH_rr_inc>;
   def : CVStrriPat<post_store, CV_SW_rr_inc>;
 
   def : CVStrrPat<truncstorei8, CV_SB_rr>;