[llvm] 345a352 - [RISCV][VLOPT] Avoid crash when user produces scalar def (#120255)

[via llvm-commits]

Author: Michael Maitland
Date: 2024-12-17T12:07:29-05:00
New Revision: 345a35259ccfdc5031bc4c4bdb0f47959fa75806

URL: https://github.com/llvm/llvm-project/commit/345a35259ccfdc5031bc4c4bdb0f47959fa75806
DIFF: https://github.com/llvm/llvm-project/commit/345a35259ccfdc5031bc4c4bdb0f47959fa75806.diff

LOG: [RISCV][VLOPT] Avoid crash when user produces scalar def (#120255)

I found this crash when trying to enable the VLOptimizer pass. We need
this patch before we can enable by default. The old assert was not
checking that USE and DEF were vector registers. The correct condition
is guarded at the callsite of tryReduceVL.

Added: 
    llvm/test/CodeGen/RISCV/rvv/vl-opt-user-scalar-def.mir

Modified: 
    llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
index 5f330e272ad0e5..bd48d730a5704b 100644
--- a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
@@ -936,12 +936,6 @@ bool RISCVVLOptimizer::checkUsers(const MachineOperand *&CommonVL,
     }
 
     // The SEW and LMUL of destination and source registers need to match.
-
-    // We know that MI DEF is a vector register, because that was the guard
-    // to call this function.
-    assert(isVectorRegClass(UserMI.getOperand(0).getReg(), MRI) &&
-           "Expected DEF and USE to be vector registers");
-
     OperandInfo ConsumerInfo = getOperandInfo(UserOp, MRI);
     OperandInfo ProducerInfo = getOperandInfo(MI.getOperand(0), MRI);
     if (ConsumerInfo.isUnknown() || ProducerInfo.isUnknown() ||

diff  --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt-user-scalar-def.mir b/llvm/test/CodeGen/RISCV/rvv/vl-opt-user-scalar-def.mir
new file mode 100644
index 00000000000000..eeec39ac5cfae5
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt-user-scalar-def.mir
@@ -0,0 +1,15 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc %s -o - -mtriple=riscv32 -mattr=+v -run-pass=riscv-vl-optimizer -verify-machineinstrs | FileCheck %s
+
+---
+name:            vec_instr_with_scalar_def
+tracksRegLiveness: true
+isSSA:           true
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: vec_instr_with_scalar_def
+    ; CHECK: [[PseudoVMNAND_MM_B8_:%[0-9]+]]:vr = PseudoVMNAND_MM_B8 $noreg, $noreg, -1, 0 /* e8 */
+    ; CHECK-NEXT: [[PseudoVCPOP_M_B1_:%[0-9]+]]:gpr = PseudoVCPOP_M_B1 killed [[PseudoVMNAND_MM_B8_]], -1, 0 /* e8 */
+    %1:vr = PseudoVMNAND_MM_B8 $noreg, $noreg, -1, 0 /* e8 */
+    %2:gpr = PseudoVCPOP_M_B1 killed %1, -1, 0 /* e8 */
+...