[llvm] [RISCV][VLOPT] Avoid crash when user produces scalar def (PR #120255)

[Luke Lau via llvm-commits]

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@@ -938,9 +938,9 @@ bool RISCVVLOptimizer::checkUsers(const MachineOperand *&CommonVL,
     // The SEW and LMUL of destination and source registers need to match.
 
     // We know that MI DEF is a vector register, because that was the guard
-    // to call this function.
-    assert(isVectorRegClass(UserMI.getOperand(0).getReg(), MRI) &&
-           "Expected DEF and USE to be vector registers");
+    // to call this function, so we don't need to assert it.
+    assert(isVectorRegClass(UserOp.getReg(), MRI) &&
+           "Expected consumed operand to be a vector register");
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lukel97 wrote:

Is UserOp.getReg() the same as MI.getOperand(0).getReg()? Which is what's guarded in the callsite at tryReduceVL? 

Should we maybe just remove this assertion entirely?

https://github.com/llvm/llvm-project/pull/120255