[llvm] [RISCV][VLOPT] Avoid crash when user produces scalar def (PR #120255)

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llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: Michael Maitland (michaelmaitland)

<details>
<summary>Changes</summary>

I found this crash when trying to enable the VLOptimizer pass. We need this patch before we can enable by default.

---
Full diff: https://github.com/llvm/llvm-project/pull/120255.diff


2 Files Affected:

- (modified) llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp (+4-4) 
- (added) llvm/test/CodeGen/RISCV/rvv/vl-opt-user-scalar-def.mir (+21) 


``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
index 5f330e272ad0e5..8c8d68fc7d8007 100644
--- a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
@@ -938,11 +938,11 @@ bool RISCVVLOptimizer::checkUsers(const MachineOperand *&CommonVL,
     // The SEW and LMUL of destination and source registers need to match.
 
     // We know that MI DEF is a vector register, because that was the guard
-    // to call this function.
-    assert(isVectorRegClass(UserMI.getOperand(0).getReg(), MRI) &&
-           "Expected DEF and USE to be vector registers");
+    // to call this function, so we don't need to assert it.
+    assert(isVectorRegClass(UserOp.getReg(), MRI) &&
+           "Expected consumed operand to be a vector register");
 
-    OperandInfo ConsumerInfo = getOperandInfo(UserOp, MRI);
+        OperandInfo ConsumerInfo = getOperandInfo(UserOp, MRI);
     OperandInfo ProducerInfo = getOperandInfo(MI.getOperand(0), MRI);
     if (ConsumerInfo.isUnknown() || ProducerInfo.isUnknown() ||
         !OperandInfo::EMULAndEEWAreEqual(ConsumerInfo, ProducerInfo)) {
diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt-user-scalar-def.mir b/llvm/test/CodeGen/RISCV/rvv/vl-opt-user-scalar-def.mir
new file mode 100644
index 00000000000000..bd4d2abb4e008c
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt-user-scalar-def.mir
@@ -0,0 +1,21 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc %s -o - -mtriple=riscv32 -mattr=+v -run-pass=riscv-vl-optimizer -verify-machineinstrs | FileCheck %s
+
+---
+name:            vec_instr_with_scalar_def
+tracksRegLiveness: true
+isSSA:           true
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: vec_instr_with_scalar_def
+    ; CHECK: [[PseudoVMNAND_MM_B8_:%[0-9]+]]:vr = PseudoVMNAND_MM_B8 $noreg, $noreg, -1, 0 /* e8 */
+    ; CHECK-NEXT: [[PseudoVCPOP_M_B1_:%[0-9]+]]:gpr = PseudoVCPOP_M_B1 killed [[PseudoVMNAND_MM_B8_]], -1, 0 /* e8 */
+    ; CHECK-NEXT: [[SLTIU:%[0-9]+]]:gpr = SLTIU killed [[PseudoVCPOP_M_B1_]], 1
+    ; CHECK-NEXT: $x10 = COPY [[SLTIU]]
+    ; CHECK-NEXT: PseudoRET implicit $x10
+    %1:vr = PseudoVMNAND_MM_B8 $noreg, $noreg, -1, 0 /* e8 */
+    %2:gpr = PseudoVCPOP_M_B1 killed %1, -1, 0 /* e8 */
+    %3:gpr = SLTIU killed %2, 1
+    $x10 = COPY %3
+    PseudoRET implicit $x10
+...

``````````

</details>


https://github.com/llvm/llvm-project/pull/120255