[llvm] [AArch64][SVE] Add partial reduction SDNodes (PR #117185)

[Paul Walker via llvm-commits]

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@@ -8147,7 +8147,7 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
 
     if (!TLI.shouldExpandPartialReductionIntrinsic(cast<IntrinsicInst>(&I))) {
       setValue(&I,
-               DAG.getNode(ISD::PARTIAL_REDUCE_UADD, dl, AccVT, Acc, Input));
+               DAG.getNode(ISD::PARTIAL_REDUCE_UMLA, dl, AccVT, Acc, Input));
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paulwalker-arm wrote:

Correct. For this initial building of the DAG I recommend ignoring the operand analysis and just always create the extra vector of ones operand.  Then you can implement a DAG combine to transform the `PARTIAL_REDUCE_UMLA` based on the operands (i.e. remove an explicit multiply and/or extensions).

https://github.com/llvm/llvm-project/pull/117185