[llvm] [AArch64][SVE] Add partial reduction SDNodes (PR #117185)

[Benjamin Maxwell via llvm-commits]

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@@ -8147,7 +8147,7 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
 
     if (!TLI.shouldExpandPartialReductionIntrinsic(cast<IntrinsicInst>(&I))) {
       setValue(&I,
-               DAG.getNode(ISD::PARTIAL_REDUCE_UADD, dl, AccVT, Acc, Input));
+               DAG.getNode(ISD::PARTIAL_REDUCE_UMLA, dl, AccVT, Acc, Input));
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MacDue wrote:

What are the semantics of `PARTIAL_REDUCE_UMLA`? I thought it meant unsigned multiply-accumulate. In which case, I'd expect it to take two inputs and an accumulator, it multiplies the inputs together and then accumulates them. 

If so, I think here you would not be able to directly lower a partial_reduce.add to a `PARTIAL_REDUCE_UMLA`. You would need to check the the MUL on the input, then use the operands of the MUL as your inputs. If there was no MUL, you'd need to set one of the inputs to a constant splat of all ones. 



https://github.com/llvm/llvm-project/pull/117185