[llvm] RegAllocGreedy: Fix subrange based instruction split logic (PR #120199)

[Quentin Colombet via llvm-commits]

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@@ -1344,37 +1344,7 @@ static unsigned getNumAllocatableRegsForConstraints(
   return RCI.getNumAllocatableRegs(ConstrainedRC);
 }
 
-static LaneBitmask getInstReadLaneMask(const MachineRegisterInfo &MRI,
-                                       const TargetRegisterInfo &TRI,
-                                       const MachineInstr &FirstMI,
-                                       Register Reg) {
-  LaneBitmask Mask;
-  SmallVector<std::pair<MachineInstr *, unsigned>, 8> Ops;
-  (void)AnalyzeVirtRegInBundle(const_cast<MachineInstr &>(FirstMI), Reg, &Ops);
-
-  for (auto [MI, OpIdx] : Ops) {
-    const MachineOperand &MO = MI->getOperand(OpIdx);
-    assert(MO.isReg() && MO.getReg() == Reg);
-    unsigned SubReg = MO.getSubReg();
-    if (SubReg == 0 && MO.isUse()) {
-      if (MO.isUndef())
-        continue;
-      return MRI.getMaxLaneMaskForVReg(Reg);
-    }
-
-    LaneBitmask SubRegMask = TRI.getSubRegIndexLaneMask(SubReg);
-    if (MO.isDef()) {
-      if (!MO.isUndef())
-        Mask |= ~SubRegMask;
-    } else
-      Mask |= SubRegMask;
-  }
-
-  return Mask;
-}
-
-/// Return true if \p MI at \P Use reads a subset of the lanes live in \p
-/// VirtReg.
+/// Return true if \p MI at \P Use reads a subset of the lanes of \p VirtReg.
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qcolombet wrote:

`Use` is unused now.

https://github.com/llvm/llvm-project/pull/120199